From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,T_DKIMWL_WL_HIGH,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BAEEC072B1 for ; Thu, 30 May 2019 04:20:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 35F65252F6 for ; Thu, 30 May 2019 04:20:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1559190032; bh=+n9P5jighs7ry8zd1sXze259asg1PsT25vC4Zi044LI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=vh+QbdEDVTH+6ss7HTT8s71S3pBxkn9LG3EIAi2pgOscCSvvrdDo78/K5/xH/r1Sl nAVpaUvSp23S1usiZC0enBkzTN31VXpHYWtWGYrkQF0f0QH/Q+4RAzirj4Q7zuqHVa ysiqBTreLvbHan2VrJvIETqrN58+nmy4LoWDmw1I= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729368AbfE3EUX (ORCPT ); Thu, 30 May 2019 00:20:23 -0400 Received: from mail.kernel.org ([198.145.29.99]:38048 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730230AbfE3DPU (ORCPT ); Wed, 29 May 2019 23:15:20 -0400 Received: from localhost (ip67-88-213-2.z213-88-67.customer.algx.net [67.88.213.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 521CB245B3; Thu, 30 May 2019 03:15:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1559186120; bh=+n9P5jighs7ry8zd1sXze259asg1PsT25vC4Zi044LI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JYCzGQvuN0+mnQR1BuCZtaEe7JvAT5zYOqxgUSF7Id/RoBYqZHAxmW9Hl/Ifrfwj6 FL/V8gbqWJkZX22rLK/PNznwY+3v+2D79dKTwz6/+Rmv1ZvSP/ISztOJTbVghJFvzf D/wLP9Vvfm+FJjU6A9h4c9munnj+ofYZWV/MTSQU= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Ludovic Barre , Mark Brown , Sasha Levin Subject: [PATCH 5.0 275/346] spi: stm32-qspi: add spi_master_put in release function Date: Wed, 29 May 2019 20:05:48 -0700 Message-Id: <20190530030554.877122272@linuxfoundation.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190530030540.363386121@linuxfoundation.org> References: <20190530030540.363386121@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org [ Upstream commit a88eceb17ac7e8dc4ad9995681af61c8371668f4 ] This patch adds spi_master_put in release function to drop the controller's refcount. Signed-off-by: Ludovic Barre Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/spi/spi-stm32-qspi.c | 46 ++++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c index 3b2a9a6b990da..0b9a8bddb939d 100644 --- a/drivers/spi/spi-stm32-qspi.c +++ b/drivers/spi/spi-stm32-qspi.c @@ -93,6 +93,7 @@ struct stm32_qspi_flash { struct stm32_qspi { struct device *dev; + struct spi_controller *ctrl; void __iomem *io_base; void __iomem *mm_base; resource_size_t mm_size; @@ -397,6 +398,7 @@ static void stm32_qspi_release(struct stm32_qspi *qspi) writel_relaxed(0, qspi->io_base + QSPI_CR); mutex_destroy(&qspi->lock); clk_disable_unprepare(qspi->clk); + spi_master_put(qspi->ctrl); } static int stm32_qspi_probe(struct platform_device *pdev) @@ -413,43 +415,54 @@ static int stm32_qspi_probe(struct platform_device *pdev) return -ENOMEM; qspi = spi_controller_get_devdata(ctrl); + qspi->ctrl = ctrl; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi"); qspi->io_base = devm_ioremap_resource(dev, res); - if (IS_ERR(qspi->io_base)) - return PTR_ERR(qspi->io_base); + if (IS_ERR(qspi->io_base)) { + ret = PTR_ERR(qspi->io_base); + goto err; + } res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm"); qspi->mm_base = devm_ioremap_resource(dev, res); - if (IS_ERR(qspi->mm_base)) - return PTR_ERR(qspi->mm_base); + if (IS_ERR(qspi->mm_base)) { + ret = PTR_ERR(qspi->mm_base); + goto err; + } qspi->mm_size = resource_size(res); - if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) - return -EINVAL; + if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) { + ret = -EINVAL; + goto err; + } irq = platform_get_irq(pdev, 0); ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0, dev_name(dev), qspi); if (ret) { dev_err(dev, "failed to request irq\n"); - return ret; + goto err; } init_completion(&qspi->data_completion); qspi->clk = devm_clk_get(dev, NULL); - if (IS_ERR(qspi->clk)) - return PTR_ERR(qspi->clk); + if (IS_ERR(qspi->clk)) { + ret = PTR_ERR(qspi->clk); + goto err; + } qspi->clk_rate = clk_get_rate(qspi->clk); - if (!qspi->clk_rate) - return -EINVAL; + if (!qspi->clk_rate) { + ret = -EINVAL; + goto err; + } ret = clk_prepare_enable(qspi->clk); if (ret) { dev_err(dev, "can not enable the clock\n"); - return ret; + goto err; } rstc = devm_reset_control_get_exclusive(dev, NULL); @@ -472,14 +485,11 @@ static int stm32_qspi_probe(struct platform_device *pdev) ctrl->dev.of_node = dev->of_node; ret = devm_spi_register_master(dev, ctrl); - if (ret) - goto err_spi_register; - - return 0; + if (!ret) + return 0; -err_spi_register: +err: stm32_qspi_release(qspi); - return ret; } -- 2.20.1