From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,T_DKIMWL_WL_HIGH,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB926C468BD for ; Sat, 8 Jun 2019 11:45:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 81FCE214DA for ; Sat, 8 Jun 2019 11:45:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1559994351; bh=IAPHIq4ehYFHnH/Bp/L79kijziW97T6Yf4romK7Qzxc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=UOv/aWWiqj55LaPIS0RHUcwhxDMv5WqnzuMJ6iicwo9js5Y+FN8XFgAR90RjLyk2y TML4lFsJAZ9xoHqhVspoLrOh2CK3zs/vG/JC+Bow2LBC4I3PNHj5DsR4SY5s2wbYEX CgMW8zlfDlIjeBiDf63I9Be46OFW3cbaGpkw03AY= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728681AbfFHLnQ (ORCPT ); Sat, 8 Jun 2019 07:43:16 -0400 Received: from mail.kernel.org ([198.145.29.99]:60506 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728672AbfFHLnP (ORCPT ); Sat, 8 Jun 2019 07:43:15 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 1B53E214C6; Sat, 8 Jun 2019 11:43:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1559994195; bh=IAPHIq4ehYFHnH/Bp/L79kijziW97T6Yf4romK7Qzxc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UaOdHYtedrKms1a+nUKqk/nW48pcdFf3vVdXkXByzDVz2e4E9Tw7h/By4WzQL+l8f flhQsKPVGCLuSEsLdluJkNfcWrgHL+7ezv8VTCmICvaSLEgZp/ZpaQcyGT9OkyoWzv sMwybPgLHmkG8eb5JtIXxBdkYijnmKZiCgvlx8mg= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Frank van der Linden , Borislav Petkov , Andy Lutomirski , Linus Torvalds , Peter Zijlstra , Thomas Gleixner , bp@alien8.de, jiaxun.yang@flygoat.com, Ingo Molnar , Sasha Levin Subject: [PATCH AUTOSEL 4.19 12/49] x86/CPU/AMD: Don't force the CPB cap when running under a hypervisor Date: Sat, 8 Jun 2019 07:41:53 -0400 Message-Id: <20190608114232.8731-12-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190608114232.8731-1-sashal@kernel.org> References: <20190608114232.8731-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Frank van der Linden [ Upstream commit 2ac44ab608705948564791ce1d15d43ba81a1e38 ] For F17h AMD CPUs, the CPB capability ('Core Performance Boost') is forcibly set, because some versions of that chip incorrectly report that they do not have it. However, a hypervisor may filter out the CPB capability, for good reasons. For example, KVM currently does not emulate setting the CPB bit in MSR_K7_HWCR, and unchecked MSR access errors will be thrown when trying to set it as a guest: unchecked MSR access error: WRMSR to 0xc0010015 (tried to write 0x0000000001000011) at rIP: 0xffffffff890638f4 (native_write_msr+0x4/0x20) Call Trace: boost_set_msr+0x50/0x80 [acpi_cpufreq] cpuhp_invoke_callback+0x86/0x560 sort_range+0x20/0x20 cpuhp_thread_fun+0xb0/0x110 smpboot_thread_fn+0xef/0x160 kthread+0x113/0x130 kthread_create_worker_on_cpu+0x70/0x70 ret_from_fork+0x35/0x40 To avoid this issue, don't forcibly set the CPB capability for a CPU when running under a hypervisor. Signed-off-by: Frank van der Linden Acked-by: Borislav Petkov Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: bp@alien8.de Cc: jiaxun.yang@flygoat.com Fixes: 0237199186e7 ("x86/CPU/AMD: Set the CPB bit unconditionally on F17h") Link: http://lkml.kernel.org/r/20190522221745.GA15789@dev-dsk-fllinden-2c-c1893d73.us-west-2.amazon.com [ Minor edits to the changelog. ] Signed-off-by: Ingo Molnar Signed-off-by: Sasha Levin --- arch/x86/kernel/cpu/amd.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 6a25278e0092..da1f5e78363e 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -819,8 +819,11 @@ static void init_amd_zn(struct cpuinfo_x86 *c) { set_cpu_cap(c, X86_FEATURE_ZEN); - /* Fix erratum 1076: CPB feature bit not being set in CPUID. */ - if (!cpu_has(c, X86_FEATURE_CPB)) + /* + * Fix erratum 1076: CPB feature bit not being set in CPUID. + * Always set it, except when running under a hypervisor. + */ + if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_CPB)) set_cpu_cap(c, X86_FEATURE_CPB); } -- 2.20.1