From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section
Date: Thu, 18 Jul 2019 12:14:30 -0700 [thread overview]
Message-ID: <20190718191430.GB30177@intel.com> (raw)
In-Reply-To: <20190717223451.2595-1-dhinakaran.pandiyan@intel.com>
On Wed, Jul 17, 2019 at 03:34:51PM -0700, Dhinakaran Pandiyan wrote:
> A single 32-bit PSR2 training pattern field follows the sixteen element
> array of PSR table entries in the VBT spec. But, we incorrectly define
> this PSR2 field for each of the PSR table entries. As a result, the PSR1
> training pattern duration for any panel_type != 0 will be parsed
> incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
> version >= 226 will also be wrong.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: stable@vger.kernel.org
> Cc: stable@vger.kernel.org #v5.2
> Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111088
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204183
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Tested-by: François Guerraz <kubrick@fgv6.net>
pushed, thanks for the patches, reviews and tests.
> ---
> Drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 21501d565327..b416b394b641 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
> }
>
> if (bdb->version >= 226) {
> - u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
> + u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
>
> wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
> switch (wakeup_time) {
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 93f5c9d204d6..09cd37fb0b1c 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -481,13 +481,13 @@ struct psr_table {
> /* TP wake up time in multiple of 100 */
> u16 tp1_wakeup_time;
> u16 tp2_tp3_wakeup_time;
> -
> - /* PSR2 TP2/TP3 wakeup time for 16 panels */
> - u32 psr2_tp2_tp3_wakeup_time;
> } __packed;
>
> struct bdb_psr {
> struct psr_table psr_table[16];
> +
> + /* PSR2 TP2/TP3 wakeup time for 16 panels */
> + u32 psr2_tp2_tp3_wakeup_time;
> } __packed;
>
> /*
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-07-18 19:13 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-17 22:34 [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section Dhinakaran Pandiyan
2019-07-18 19:14 ` Rodrigo Vivi [this message]
[not found] ` <20190719004526.B0CC521850@mail.kernel.org>
2019-07-22 23:13 ` [PATCH stable v5.2] " Dhinakaran Pandiyan
2019-07-24 12:06 ` Greg KH
2019-07-24 17:27 ` Souza, Jose
2019-07-24 17:40 ` [Intel-gfx] " Rodrigo Vivi
2019-07-30 15:19 ` Rodrigo Vivi
2019-07-30 15:27 ` Greg KH
2019-07-30 16:22 ` Rodrigo Vivi
2019-07-30 16:27 ` Greg KH
2019-07-30 16:56 ` Rodrigo Vivi
2019-07-30 17:08 ` Greg KH
2019-07-30 18:24 ` Pandiyan, Dhinakaran
2019-07-30 20:42 ` [Intel-gfx] [PATCH] " Rodrigo Vivi
2019-07-30 21:48 ` Sasha Levin
2019-07-31 17:14 ` Vivi, Rodrigo
2019-07-31 19:23 ` Sasha Levin
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