From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC570C76197 for ; Fri, 19 Jul 2019 04:29:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AD8682082E for ; Fri, 19 Jul 2019 04:29:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563510558; bh=ItxFliTD6WeA+ql+n36UYHQERTf9F0u/4k5yMPa57MM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=anQiGxt7IQbLcafNo8/mmqQJvYKK3KZ2h2hyPRgGGVIzJc0xC38eQIZQRsHKeTNvj 2O8tscpTx+OaVV1tcUBz6jPqBpvcxHeQP/eGFBT8v9uX2icXemyl+dfRbFv52sYPPx 2FWZ6icbY7D3C4t2c4VXhwODoYlMRpmu2cuuNNtg= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729347AbfGSE3O (ORCPT ); Fri, 19 Jul 2019 00:29:14 -0400 Received: from mail.kernel.org ([198.145.29.99]:38304 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730603AbfGSEFo (ORCPT ); Fri, 19 Jul 2019 00:05:44 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id BDD7B21873; Fri, 19 Jul 2019 04:05:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563509143; bh=ItxFliTD6WeA+ql+n36UYHQERTf9F0u/4k5yMPa57MM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QVH3uwIyovMqL7WvabH8GEOnXO7Ej3zpKXYTkn5eWDDn+/SQcP7ctlkp6UJZ5uZTr CQwGRxETQYhUHiViEz19RLCllatjghEWgYAsANvb2zqRyyYO8U75XuAIa6HzSzsbFs CKg8gXAqVadmSMxKTGu9+Mic+c91KPYP+dA74hQk= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Hou Zhiqiang , Lorenzo Pieralisi , Minghuan Lian , Subrahmanya Lingappa , Sasha Levin , linux-pci@vger.kernel.org Subject: [PATCH AUTOSEL 5.1 095/141] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions Date: Fri, 19 Jul 2019 00:02:00 -0400 Message-Id: <20190719040246.15945-95-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190719040246.15945-1-sashal@kernel.org> References: <20190719040246.15945-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Hou Zhiqiang [ Upstream commit f7fee1b42fe4f8171a4b1cad05c61907c33c53f6 ] The inbound and outbound windows have completely separate control registers sets in the host controller MMIO space. Windows control register are accessed through an MMIO base address and an offset that depends on the window index. Since inbound and outbound windows control registers are completely separate there is no real need to use different window indexes in the inbound/outbound windows initialization routines to prevent clashing. To fix this inconsistency, change the MEM inbound window index to 0, mirroring the outbound window set-up. Signed-off-by: Hou Zhiqiang [lorenzo.pieralisi@arm.com: update commit log] Signed-off-by: Lorenzo Pieralisi Reviewed-by: Minghuan Lian Reviewed-by: Subrahmanya Lingappa Signed-off-by: Sasha Levin --- drivers/pci/controller/pcie-mobiveil.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index e4a1964e1b43..387a20f3c240 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -546,7 +546,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) resource_size(pcie->ob_io_res)); /* memory inbound translation window */ - program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); + program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); /* Get the I/O and memory ranges from DT */ resource_list_for_each_entry_safe(win, tmp, &pcie->resources) { -- 2.20.1