From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4ADEEC76186 for ; Wed, 24 Jul 2019 20:18:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1E147214AF for ; Wed, 24 Jul 2019 20:18:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563999483; bh=CXM5VbJynbXTdT62wnQeXlfAn8i6CZymbpkKpf8OkyI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=GJQHG7L3lhmquHRbGBVWVX/tP/sDqPcOhkpQGjjK4fOkgl6YmZzIwYNM/K/ivij6P uLIIoC1jDjwWnBNmyUb6q9V6fRfUiD1Y+em5ys28WwBLfsX4uABgyDkZNzISJ91oHo BOV6fjg3X/ckB66p7Y5JO4j8ZAdIlK/adNeRPI1A= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391273AbfGXTtl (ORCPT ); Wed, 24 Jul 2019 15:49:41 -0400 Received: from mail.kernel.org ([198.145.29.99]:57914 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390800AbfGXTtk (ORCPT ); Wed, 24 Jul 2019 15:49:40 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 84ED920659; Wed, 24 Jul 2019 19:49:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563997779; bh=CXM5VbJynbXTdT62wnQeXlfAn8i6CZymbpkKpf8OkyI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NZ4wU0aRDNLplV7yBMT3/bw0373BVSZqE2KtKHyAUvoz3FsBpO/LRHvCH6Y0e/yrO wqVH2ZYQ7VLk5umIhigT3pMdsZKD8mRWY1gwG3iHcHKN/pf27tPQkKTXUuxHL53Rof uKEwTEzbTBfM7zn92C03QZdXuQp03trxsnoqpe2Q= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Icenowy Zheng , Ondrej Jirman , "David S. Miller" , Sasha Levin Subject: [PATCH 5.1 140/371] net: stmmac: sun8i: force select external PHY when no internal one Date: Wed, 24 Jul 2019 21:18:12 +0200 Message-Id: <20190724191735.534078181@linuxfoundation.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190724191724.382593077@linuxfoundation.org> References: <20190724191724.382593077@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org [ Upstream commit 0fec7e72ae1391bb2d7527efb54fe6ae88acabce ] The PHY selection bit also exists on SoCs without an internal PHY; if it's set to 1 (internal PHY, default value) then the MAC will not make use of any PHY on such SoCs. This problem appears when adapting for H6, which has no real internal PHY (the "internal PHY" on H6 is not on-die, but on a co-packaged AC200 chip, connected via RMII interface at GPIO bank A). Force the PHY selection bit to 0 when the SOC doesn't have an internal PHY, to address the problem of a wrong default value. Signed-off-by: Icenowy Zheng Signed-off-by: Ondrej Jirman Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index ba124a4da793..8325e6499739 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -893,6 +893,11 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) * address. No need to mask it again. */ reg |= 1 << H3_EPHY_ADDR_SHIFT; + } else { + /* For SoCs without internal PHY the PHY selection bit should be + * set to 0 (external PHY). + */ + reg &= ~H3_EPHY_SELECT; } if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { -- 2.20.1