From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 623E1C0650F for ; Mon, 5 Aug 2019 13:30:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2E04B20651 for ; Mon, 5 Aug 2019 13:30:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1565011830; bh=NiODZww1Lx7CncHNndOsLnpgx9qKu/NV6F80uKpbQqk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=xuioFlA+idit1sE6c2nPNHTXDqxJEQKB7JUV9EVvqUhSpOHgMAphbsl/h/E4vdoNY UIx+H51m+tH8ezswYYMQ1Z78vmSW/Vxxktv4M8E5HDK9R/FZUYPb2+hmsWUDTcKPVp QobLPfnZP6BzgWSEr+UM3u+eJOur0Ie4a064+qVc= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730298AbfHENUl (ORCPT ); Mon, 5 Aug 2019 09:20:41 -0400 Received: from mail.kernel.org ([198.145.29.99]:56734 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729773AbfHENUj (ORCPT ); Mon, 5 Aug 2019 09:20:39 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A25522075B; Mon, 5 Aug 2019 13:20:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1565011238; bh=NiODZww1Lx7CncHNndOsLnpgx9qKu/NV6F80uKpbQqk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=0xHXnB1S2VH7fBPIFI0lk+XyymZYIYquiKtO3WGs/C6fi7HU/A1p6jcbJpJI4Pkvz PwxbFThzO9HPnXdw4MWe1B2zokKr/B06yCNEG3bGCW80ZWSvPChbsGqJFWg0QtUeWw bgpeZLGhpjU57jPW5XtOzJVSSJGh0TmUOaEnJag4= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Andy Gross , Niklas Cassel , Vinod Koul , Olof Johansson , Sasha Levin Subject: [PATCH 5.2 017/131] arm64: qcom: qcs404: Add reset-cells to GCC node Date: Mon, 5 Aug 2019 15:01:44 +0200 Message-Id: <20190805124952.589825090@linuxfoundation.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190805124951.453337465@linuxfoundation.org> References: <20190805124951.453337465@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org [ Upstream commit 0763d0c2273a3c72247d325c48fbac3d918d6b87 ] This patch adds a reset-cells property to the gcc controller on the QCS404. Without this in place, we get warnings like the following if nodes reference a gcc reset: arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property): /soc@0/remoteproc@b00000: Missing property '#reset-cells' in node /soc@0/clock-controller@1800000 or bad phandle (referred from resets[0]) also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3 DTC arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property): /soc@0/remoteproc@b00000: Missing property '#reset-cells' in node /soc@0/clock-controller@1800000 or bad phandle (referred from resets[0]) also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3 Signed-off-by: Andy Gross Reviewed-by: Niklas Cassel Reviewed-by: Vinod Koul Signed-off-by: Olof Johansson Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index ffedf9640af7d..65a2cbeb28bec 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -383,6 +383,7 @@ compatible = "qcom,gcc-qcs404"; reg = <0x01800000 0x80000>; #clock-cells = <1>; + #reset-cells = <1>; assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; -- 2.20.1