From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9ABEC4CEC9 for ; Wed, 18 Sep 2019 06:29:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B61B121906 for ; Wed, 18 Sep 2019 06:29:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1568788152; bh=mqrNHnKR9H8wgI/Eov6wPy08jIg4/CyN6kxoTRpegyU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=tkx4Bjxr9jFcjdL7LMLKeazwm78cgeEHyNLE/fYkSEs83vg9XuuLD8aHjYbu+bade NHBegvdW3me3xkqZQY2CQ5acbg/s+TYB7/EZkc69AKARqzigq8z7ODgP3sfiXSKAq0 M5SYnjBH6SGKKPDaIFeYqrxFU3BE7jWYElIq/XIk= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728846AbfIRG0b (ORCPT ); Wed, 18 Sep 2019 02:26:31 -0400 Received: from mail.kernel.org ([198.145.29.99]:47898 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727337AbfIRG02 (ORCPT ); Wed, 18 Sep 2019 02:26:28 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6F79D218AF; Wed, 18 Sep 2019 06:26:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1568787987; bh=mqrNHnKR9H8wgI/Eov6wPy08jIg4/CyN6kxoTRpegyU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eHc9kam2ERuGkZhj+RcXYfJAWsYbJox4zqezpdNC2wHFk67ccqlh+NfyW620hJJDB wW9AhVL69E+1QSlONfeAok9JDSZqAGc1kptW4o83cSUpSnb9QmhZM2tXy204uUMcAa OSm9wgz4GJCf3EMtLd+fEfieMdUirgTMuI5bSMK0= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Douglas Anderson , Heiko Stuebner Subject: [PATCH 5.2 58/85] clk: rockchip: Dont yell about bad mmc phases when getting Date: Wed, 18 Sep 2019 08:19:16 +0200 Message-Id: <20190918061235.943581380@linuxfoundation.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190918061234.107708857@linuxfoundation.org> References: <20190918061234.107708857@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Douglas Anderson commit 6943b839721ad4a31ad2bacf6e71b21f2dfe3134 upstream. At boot time, my rk3288-veyron devices yell with 8 lines that look like this: [ 0.000000] rockchip_mmc_get_phase: invalid clk rate This is because the clock framework at clk_register() time tries to get the phase but we don't have a parent yet. While the errors appear to be harmless they are still ugly and, in general, we don't want yells like this in the log unless they are important. There's no real reason to be yelling here. We can still return -EINVAL to indicate that the phase makes no sense without a parent. If someone really tries to do tuning and the clock is reported as 0 then we'll see the yells in rockchip_mmc_set_phase(). Fixes: 4bf59902b500 ("clk: rockchip: Prevent calculating mmc phase if clock rate is zero") Signed-off-by: Douglas Anderson Signed-off-by: Heiko Stuebner Signed-off-by: Greg Kroah-Hartman --- drivers/clk/rockchip/clk-mmc-phase.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) --- a/drivers/clk/rockchip/clk-mmc-phase.c +++ b/drivers/clk/rockchip/clk-mmc-phase.c @@ -52,10 +52,8 @@ static int rockchip_mmc_get_phase(struct u32 delay_num = 0; /* See the comment for rockchip_mmc_set_phase below */ - if (!rate) { - pr_err("%s: invalid clk rate\n", __func__); + if (!rate) return -EINVAL; - } raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);