From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC321C32792 for ; Thu, 3 Oct 2019 17:36:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C55192086A for ; Thu, 3 Oct 2019 17:36:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1570124166; bh=8LVBhwOe9iKmTrHRY8JxBQfug0KuqOv9YxaYUxIzXu8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=zBlX4XlG95SNjrcBZYHDY9pdaoTKQQBfU+9L/91q37G9O3DmQ3r++FwRmyrAk9D+j oW00/XAgFGJmHCbTGjFPzz0MxNFCZJgvFw4sxSac+1qxZtz0yG273BfmDsr8AcJpiM d4P8p/LTM/xT6AcaaGpt+sQa43+UjYgh1XctVySY= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732642AbfJCRgC (ORCPT ); Thu, 3 Oct 2019 13:36:02 -0400 Received: from mail.kernel.org ([198.145.29.99]:51884 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732198AbfJCQFT (ORCPT ); Thu, 3 Oct 2019 12:05:19 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 13A99215EA; Thu, 3 Oct 2019 16:05:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1570118718; bh=8LVBhwOe9iKmTrHRY8JxBQfug0KuqOv9YxaYUxIzXu8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=x/HkxdFkFQ34TC4G88d40M2JcCAqesgXL4QxvstQUYqc6VDf2+FrixZ6Y0c5N8Ak2 Fa1VSPI6AynLy308Qc6MA7Iyb3OfFb3MjV+lWxAxsaFh1dXkrPFg8ynizSVtz16kBy 3LO2M1eSaXX0VzRLd6W7ovabxzAY8/9BQ9QmMvRA= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Mark Rutland , Catalin Marinas , James Morse , Will Deacon , Sasha Levin Subject: [PATCH 4.9 076/129] arm64: kpti: ensure patched kernel text is fetched from PoU Date: Thu, 3 Oct 2019 17:53:19 +0200 Message-Id: <20191003154353.011305485@linuxfoundation.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191003154318.081116689@linuxfoundation.org> References: <20191003154318.081116689@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Mark Rutland [ Upstream commit f32c7a8e45105bd0af76872bf6eef0438ff12fb2 ] While the MMUs is disabled, I-cache speculation can result in instructions being fetched from the PoC. During boot we may patch instructions (e.g. for alternatives and jump labels), and these may be dirty at the PoU (and stale at the PoC). Thus, while the MMU is disabled in the KPTI pagetable fixup code we may load stale instructions into the I-cache, potentially leading to subsequent crashes when executing regions of code which have been modified at runtime. Similarly to commit: 8ec41987436d566f ("arm64: mm: ensure patched kernel text is fetched from PoU") ... we can invalidate the I-cache after enabling the MMU to prevent such issues. The KPTI pagetable fixup code itself should be clean to the PoC per the boot protocol, so no maintenance is required for this code. Signed-off-by: Mark Rutland Cc: Catalin Marinas Reviewed-by: James Morse Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- arch/arm64/mm/proc.S | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 3ceec224d3d24..3b95e3126eebb 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -263,6 +263,15 @@ skip_pgd: msr sctlr_el1, x18 isb + /* + * Invalidate the local I-cache so that any instructions fetched + * speculatively from the PoC are discarded, since they may have + * been dynamically patched at the PoU. + */ + ic iallu + dsb nsh + isb + /* Set the flag to zero to indicate that we're all done */ str wzr, [flag_ptr] ret -- 2.20.1