Re: FAILED: patch "[PATCH] riscv: Avoid interrupts being erroneously enabled in" failed to apply to 5.3-stable tree

[Sasha Levin <sashal@kernel.org>]

On Tue, Oct 08, 2019 at 07:27:44PM +0200, gregkh@linuxfoundation.org wrote:
>
>The patch below does not apply to the 5.3-stable tree.
>If someone wants it applied there, or to any other stable or longterm
>tree, then please email the backport, including the original git commit
>id to <stable@vger.kernel.org>.
>
>thanks,
>
>greg k-h
>
>------------------ original commit in Linus's tree ------------------
>
>From c82dd6d078a2bb29d41eda032bb96d05699a524d Mon Sep 17 00:00:00 2001
>From: Vincent Chen <vincent.chen@sifive.com>
>Date: Mon, 16 Sep 2019 16:47:41 +0800
>Subject: [PATCH] riscv: Avoid interrupts being erroneously enabled in
> handle_exception()
>
>When the handle_exception function addresses an exception, the interrupts
>will be unconditionally enabled after finishing the context save. However,
>It may erroneously enable the interrupts if the interrupts are disabled
>before entering the handle_exception.
>
>For example, one of the WARN_ON() condition is satisfied in the scheduling
>where the interrupt is disabled and rq.lock is locked. The WARN_ON will
>trigger a break exception and the handle_exception function will enable the
>interrupts before entering do_trap_break function. During the procedure, if
>a timer interrupt is pending, it will be taken when interrupts are enabled.
>In this case, it may cause a deadlock problem if the rq.lock is locked
>again in the timer ISR.
>
>Hence, the handle_exception() can only enable interrupts when the state of
>sstatus.SPIE is 1.
>
>This patch is tested on HiFive Unleashed board.
>
>Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
>Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>[paul.walmsley@sifive.com: updated to apply]
>Fixes: bcae803a21317 ("RISC-V: Enable IRQ during exception handling")
>Cc: David Abdurachmanov <david.abdurachmanov@sifive.com>
>Cc: stable@vger.kernel.org
>Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
>
>diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
>index 74ccfd464071..da7aa88113c2 100644
>--- a/arch/riscv/kernel/entry.S
>+++ b/arch/riscv/kernel/entry.S
>@@ -166,9 +166,13 @@ ENTRY(handle_exception)
> 	move a0, sp /* pt_regs */
> 	tail do_IRQ
> 1:
>-	/* Exceptions run with interrupts enabled */
>+	/* Exceptions run with interrupts enabled or disabled
>+	   depending on the state of sstatus.SR_SPIE */
>+	andi t0, s1, SR_SPIE
>+	beqz t0, 1f
> 	csrs CSR_SSTATUS, SR_SIE
>
>+1:

I might be missing something here, but wasn't the label "1" already
declared a few lines above?

--
Thanks,
Sasha