From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A4C2CA9EA9 for ; Fri, 18 Oct 2019 22:22:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6B43C21852 for ; Fri, 18 Oct 2019 22:22:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1571437364; bh=8h+FkDc3xXvETtsrZrbsTH8LmB+VdeBjN9RyUmQkvEs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=gXt8S5pYu/IeQLHjzNqQ5vQZB1CGzYBZakVXbm7nZmNYANybUaoBXUi0cHarr3Ppi 1pmid0vBRQFMVbYzyiMrnGWrayvGpLrroH9ujdROSlLk3015k44j3rc2XfY1wKU9Yd hYbGlan3lB4go5A+hDo6rdHJBjF0oF1/KeFduBt0= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730134AbfJRWFq (ORCPT ); Fri, 18 Oct 2019 18:05:46 -0400 Received: from mail.kernel.org ([198.145.29.99]:37654 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730077AbfJRWFq (ORCPT ); Fri, 18 Oct 2019 18:05:46 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7E460222C9; Fri, 18 Oct 2019 22:05:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1571436345; bh=8h+FkDc3xXvETtsrZrbsTH8LmB+VdeBjN9RyUmQkvEs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h3M3O6pdru5KAZx8kCZT96SRKlbQJExU9rJUUHbZHItiwrnkj0XLYufEknXVSs7Bw G8Xcz27i/+Rt8P9/OwMba1b8eDe6ClmwIz8ddBoxmZPRotZCQ+1bxM7eSjREptu3sc aKCvSYUQqMYyzXhajuIJQK52eg01vVeqcdJvQvjE= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Kan Liang , Qiuxu Zhuo , Tony Luck , Borislav Petkov , Andy Shevchenko , Aristeu Rozanski , "H. Peter Anvin" , Ingo Molnar , linux-edac , Mauro Carvalho Chehab , Megha Dey , Peter Zijlstra , Rajneesh Bhardwaj , Thomas Gleixner , x86-ml , Sasha Levin Subject: [PATCH AUTOSEL 4.19 011/100] x86/cpu: Add Atom Tremont (Jacobsville) Date: Fri, 18 Oct 2019 18:03:56 -0400 Message-Id: <20191018220525.9042-11-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191018220525.9042-1-sashal@kernel.org> References: <20191018220525.9042-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Kan Liang [ Upstream commit 00ae831dfe4474ef6029558f5eb3ef0332d80043 ] Add the Atom Tremont model number to the Intel family list. [ Tony: Also update comment at head of file to say "_X" suffix is also used for microserver parts. ] Signed-off-by: Kan Liang Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck Signed-off-by: Borislav Petkov Cc: Andy Shevchenko Cc: Aristeu Rozanski Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: linux-edac Cc: Mauro Carvalho Chehab Cc: Megha Dey Cc: Peter Zijlstra Cc: Qiuxu Zhuo Cc: Rajneesh Bhardwaj Cc: Thomas Gleixner Cc: x86-ml Link: https://lkml.kernel.org/r/20190125195902.17109-4-tony.luck@intel.com Signed-off-by: Sasha Levin --- arch/x86/include/asm/intel-family.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 5d0b72f281402..82a57d344b9bc 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -6,7 +6,7 @@ * "Big Core" Processors (Branded as Core, Xeon, etc...) * * The "_X" parts are generally the EP and EX Xeons, or the - * "Extreme" ones, like Broadwell-E. + * "Extreme" ones, like Broadwell-E, or Atom microserver. * * While adding a new CPUID for a new microarchitecture, add a new * group to keep logically sorted out in chronological order. Within @@ -80,6 +80,7 @@ #define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */ #define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */ #define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */ +#define INTEL_FAM6_ATOM_TREMONT_X 0x86 /* Jacobsville */ /* Xeon Phi */ -- 2.20.1