From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87219C432C3 for ; Fri, 15 Nov 2019 06:21:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 617B82073C for ; Fri, 15 Nov 2019 06:21:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1573798883; bh=qYyzXt7umkf9Q1uRUWIFOcGRA0/84gaxMKeaYozMFVQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=SxAByv2NN+6K8hJmn+xPsrKC2ZAsio79Weta4sfyz0riWXclC2iT5jtabtPNmCom7 2RPRijU0CzkCn14GouYoiVo2xVQgdrEajXblfqtZUs1HZ/4Z2PL9TWSzUv0npL3YC5 IO7UGkHJKzxzizOpIVIapha9uyYMPokCAl/Qf32c= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727223AbfKOGVW (ORCPT ); Fri, 15 Nov 2019 01:21:22 -0500 Received: from mail.kernel.org ([198.145.29.99]:50124 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727206AbfKOGVW (ORCPT ); Fri, 15 Nov 2019 01:21:22 -0500 Received: from localhost (unknown [104.132.150.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 49A022073A; Fri, 15 Nov 2019 06:21:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1573798881; bh=qYyzXt7umkf9Q1uRUWIFOcGRA0/84gaxMKeaYozMFVQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=enSfNf5O00CqqQQfAukEpUPhhLX8be30OhnsiNaZ11zuBE5uESVn9Zw5bFrEXRYTZ ogfTEu0Hsf4UcmCZohdk6ka2No/dTw3G5QDmUT45DfaHZCRk2gkMW8SpR6+xgQo0tJ tcWommAEqMQfcLCJOmqwHPc227Ony3klDClDCZJQ= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Pawan Gupta , Borislav Petkov , Thomas Gleixner , Neelima Krishnan , Tony Luck , Josh Poimboeuf , Ben Hutchings Subject: [PATCH 4.4 15/20] kvm/x86: Export MDS_NO=0 to guests when TSX is enabled Date: Fri, 15 Nov 2019 14:20:44 +0800 Message-Id: <20191115062013.337413821@linuxfoundation.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191115062006.854443935@linuxfoundation.org> References: <20191115062006.854443935@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Pawan Gupta commit e1d38b63acd843cfdd4222bf19a26700fd5c699e upstream. Export the IA32_ARCH_CAPABILITIES MSR bit MDS_NO=0 to guests on TSX Async Abort(TAA) affected hosts that have TSX enabled and updated microcode. This is required so that the guests don't complain, "Vulnerable: Clear CPU buffers attempted, no microcode" when the host has the updated microcode to clear CPU buffers. Microcode update also adds support for MSR_IA32_TSX_CTRL which is enumerated by the ARCH_CAP_TSX_CTRL bit in IA32_ARCH_CAPABILITIES MSR. Guests can't do this check themselves when the ARCH_CAP_TSX_CTRL bit is not exported to the guests. In this case export MDS_NO=0 to the guests. When guests have CPUID.MD_CLEAR=1, they deploy MDS mitigation which also mitigates TAA. Signed-off-by: Pawan Gupta Signed-off-by: Borislav Petkov Signed-off-by: Thomas Gleixner Tested-by: Neelima Krishnan Reviewed-by: Tony Luck Reviewed-by: Josh Poimboeuf Signed-off-by: Ben Hutchings Signed-off-by: Greg Kroah-Hartman --- arch/x86/kvm/x86.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1008,6 +1008,25 @@ u64 kvm_get_arch_capabilities(void) if (!boot_cpu_has_bug(X86_BUG_MDS)) data |= ARCH_CAP_MDS_NO; + /* + * On TAA affected systems, export MDS_NO=0 when: + * - TSX is enabled on the host, i.e. X86_FEATURE_RTM=1. + * - Updated microcode is present. This is detected by + * the presence of ARCH_CAP_TSX_CTRL_MSR and ensures + * that VERW clears CPU buffers. + * + * When MDS_NO=0 is exported, guests deploy clear CPU buffer + * mitigation and don't complain: + * + * "Vulnerable: Clear CPU buffers attempted, no microcode" + * + * If TSX is disabled on the system, guests are also mitigated against + * TAA and clear CPU buffer mitigation is not required for guests. + */ + if (boot_cpu_has_bug(X86_BUG_TAA) && boot_cpu_has(X86_FEATURE_RTM) && + (data & ARCH_CAP_TSX_CTRL_MSR)) + data &= ~ARCH_CAP_MDS_NO; + return data; }