From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC0BFC43215 for ; Tue, 19 Nov 2019 06:03:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9BE8920872 for ; Tue, 19 Nov 2019 06:03:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1574143413; bh=gi0fFzVngAvPuitwbmsk2jTMbC43FgfYPfful1aETBg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=LfMP8maIVTZPDrxyqLRCBZdbGtQTksnb1zBZ/4C/Myod1ygVymWhh/5FWBtWC/8cs C8X/xB1xaOoalZ++WI6VQTBkOxFnrGT1QaGASmvocGOWkcmCy8phm4LsY0htTT3JDZ YboSrPDbkOJ43EEchbWMRXHwn6W5aojBSdodZt2Y= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729675AbfKSFj7 (ORCPT ); Tue, 19 Nov 2019 00:39:59 -0500 Received: from mail.kernel.org ([198.145.29.99]:34030 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730047AbfKSFj6 (ORCPT ); Tue, 19 Nov 2019 00:39:58 -0500 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 310B321783; Tue, 19 Nov 2019 05:39:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1574141997; bh=gi0fFzVngAvPuitwbmsk2jTMbC43FgfYPfful1aETBg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=1BScpzgQ7Hn6NiPYUobT4V0wmSpWSyuJfX5v3UDbVzGVWrNuw8EnPLp5z+FF7GK8B Y1oQ5T0EWPcDSvnFDvDQSzL4zPvG2aQSoTEeaUWmNN1JQTolzgt+yJprxX5rV+hk6C AN0OEBcLZF629I37kYuPzQpMTgmVF7LOL7xtZDH4= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Mathieu Poirier , Mike Leach , Leo Yan , Sasha Levin Subject: [PATCH 4.19 350/422] coresight: tmc: Fix byte-address alignment for RRP Date: Tue, 19 Nov 2019 06:19:07 +0100 Message-Id: <20191119051421.693240152@linuxfoundation.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191119051400.261610025@linuxfoundation.org> References: <20191119051400.261610025@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Leo Yan [ Upstream commit e7753f3937610633a540f2be81be87531f96ff04 ] >>From the comment in the code, it claims the requirement for byte-address alignment for RRP register: 'for 32-bit, 64-bit and 128-bit wide trace memory, the four LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must be 0s'. This isn't consistent with the program, the program sets five LSBs as zeros for 32/64/128-bit wide trace memory and set six LSBs zeros for 256-bit wide trace memory. After checking with the CoreSight Trace Memory Controller technical reference manual (ARM DDI 0461B, section 3.3.4 RAM Read Pointer Register), it proves the comment is right and the program does wrong setting. This patch fixes byte-address alignment for RRP by following correct definition in the technical reference manual. Cc: Mathieu Poirier Cc: Mike Leach Signed-off-by: Leo Yan Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 0549249f4b398..e31061308e19e 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -438,10 +438,10 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev, case TMC_MEM_INTF_WIDTH_32BITS: case TMC_MEM_INTF_WIDTH_64BITS: case TMC_MEM_INTF_WIDTH_128BITS: - mask = GENMASK(31, 5); + mask = GENMASK(31, 4); break; case TMC_MEM_INTF_WIDTH_256BITS: - mask = GENMASK(31, 6); + mask = GENMASK(31, 5); break; } -- 2.20.1