From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61144C2D0DA for ; Sun, 29 Dec 2019 17:33:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3BBBF207FF for ; Sun, 29 Dec 2019 17:33:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1577640783; bh=f+oyQdJV2mvKWAwexwUt8dcxFVa+jkYNOVD3dekVTwE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=1USVzMtHcU8GQ2eNbdGKuFAlYB2o+OBbZ15GrS8eh/ofai1miAgne4iad7zTNHyZ7 BuDYT6V2B90feRfnYcxsOA8S+ybMC3Q9s5czX/h/5tCSP4Yk6DZRKkZgYQHa20z4cH 5mF3HrTjhNUo41Z4SKdtYsGtBlMQc8XMszMdLgHQ= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728054AbfL2Rc6 (ORCPT ); Sun, 29 Dec 2019 12:32:58 -0500 Received: from mail.kernel.org ([198.145.29.99]:34020 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729377AbfL2Rc5 (ORCPT ); Sun, 29 Dec 2019 12:32:57 -0500 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 97E98207FD; Sun, 29 Dec 2019 17:32:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1577640777; bh=f+oyQdJV2mvKWAwexwUt8dcxFVa+jkYNOVD3dekVTwE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S/aJxpT9XCP6XPLxiwKVOOVKubtG6+8M10T2nRM48pGYdBmKufBQVrnd7jtywI5tB zE5BUKn8ezWYPzBH/YihwQgPLdJWIeAAIkD7IwHQMwM7HFE/fAngiSHqFpuYij5T2t 93J6/P7K1gzaIfcPj0vpAUdE2kWC9oDBYb8mwlDQ= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Grygorii Strashko , Andrew Lunn , Florian Fainelli , "David S. Miller" , Sasha Levin Subject: [PATCH 4.19 095/219] net: phy: dp83867: enable robust auto-mdix Date: Sun, 29 Dec 2019 18:18:17 +0100 Message-Id: <20191229162521.892610959@linuxfoundation.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191229162508.458551679@linuxfoundation.org> References: <20191229162508.458551679@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Grygorii Strashko [ Upstream commit 5a7f08c2abb0efc9d17aff2fc75d6d3b85e622e4 ] The link detection timeouts can be observed (or link might not be detected at all) when dp83867 PHY is configured in manual mode (speed/duplex). CFG3[9] Robust Auto-MDIX option allows to significantly improve link detection in case dp83867 is configured in manual mode and reduce link detection time. As per DM: "If link partners are configured to operational modes that are not supported by normal Auto MDI/MDIX mode (like Auto-Neg versus Force 100Base-TX or Force 100Base-TX versus Force 100Base-TX), this Robust Auto MDI/MDIX mode allows MDI/MDIX resolution and prevents deadlock." Hence, enable this option by default as there are no known reasons not to do so. Signed-off-by: Grygorii Strashko Reviewed-by: Andrew Lunn Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/phy/dp83867.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index eeadfde15940..879096d3ff41 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -86,6 +86,10 @@ #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 +/* CFG3 bits */ +#define DP83867_CFG3_INT_OE BIT(7) +#define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9) + /* CFG4 bits */ #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) @@ -331,12 +335,13 @@ static int dp83867_config_init(struct phy_device *phydev) return ret; } + val = phy_read(phydev, DP83867_CFG3); /* Enable Interrupt output INT_OE in CFG3 register */ - if (phy_interrupt_is_valid(phydev)) { - val = phy_read(phydev, DP83867_CFG3); - val |= BIT(7); - phy_write(phydev, DP83867_CFG3, val); - } + if (phy_interrupt_is_valid(phydev)) + val |= DP83867_CFG3_INT_OE; + + val |= DP83867_CFG3_ROBUST_AUTO_MDIX; + phy_write(phydev, DP83867_CFG3, val); if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) dp83867_config_port_mirroring(phydev); -- 2.20.1