From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BD05C352A3 for ; Tue, 11 Feb 2020 13:42:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6473220714 for ; Tue, 11 Feb 2020 13:42:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=alien8.de header.i=@alien8.de header.b="kq0tQxmw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727653AbgBKNmP (ORCPT ); Tue, 11 Feb 2020 08:42:15 -0500 Received: from mail.skyhub.de ([5.9.137.197]:59864 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728619AbgBKNmP (ORCPT ); Tue, 11 Feb 2020 08:42:15 -0500 Received: from zn.tnic (p200300EC2F095500BD9EB4A201E18C86.dip0.t-ipconnect.de [IPv6:2003:ec:2f09:5500:bd9e:b4a2:1e1:8c86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id 633C31EC0C8A; Tue, 11 Feb 2020 14:42:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1581428532; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dosw9ntDX7QDINjNhfhbT5aAzrLjfsYCUC0faBP+Wz0=; b=kq0tQxmwUYy42AMdJOVWEyLhI5TVx/84YmySoB2IXJGHvR9gUOmxPHGocYMI9rn0v8OZrd mNswhLPkd034/yv27q3bJsZ25w71dy58PeHoUwICP5hvvC1HUInjCFK7vKNVxusYPF7I9l YItw/xOiWKc5SaQIpd5QeFq5WtfbBiU= Date: Tue, 11 Feb 2020 14:42:05 +0100 From: Borislav Petkov To: Kim Phillips Cc: Peter Zijlstra , Ingo Molnar , Ingo Molnar , Alexander Shishkin , Andi Kleen , Arnaldo Carvalho de Melo , Babu Moger , Fenghua Yu , Frank van der Linden , "H . Peter Anvin" , Huang Rui , Janakarajan Natarajan , Jan Beulich , Jiaxun Yang , Jiri Olsa , Josh Poimboeuf , Linus Torvalds , Luwei Kang , Martin =?utf-8?B?TGnFoWth?= , Matt Fleming , Michael Petlan , Namhyung Kim , Paolo Bonzini , Pawan Gupta , Suravee Suthikulpanit , Thomas Gleixner , Tom Lendacky , x86@kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH 2/2 v2 RESEND] x86/cpu/amd: Enable the fixed intructions retired free counter IRPERF Message-ID: <20200211134205.GB32279@zn.tnic> References: <20200207230427.26515-1-kim.phillips@amd.com> <20200207230427.26515-2-kim.phillips@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20200207230427.26515-2-kim.phillips@amd.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On Fri, Feb 07, 2020 at 05:04:27PM -0600, Kim Phillips wrote: > commit aaf248848db50 ("perf/x86/msr: Add AMD IRPERF (Instructions > Retired) performance counter") added support for 'perf -e msr/irperf/', > but when exercised, we always get a 0 count: > > BEFORE: > > $ sudo perf stat -e instructions,msr/irperf/ true > > Performance counter stats for 'true': > > 624,833 instructions > # 0.00 stalled cycles per insn > 0 msr/irperf/ > > It turns out it simply needs its enable bit - HWCR bit 30 - set. This patch Avoid having "This patch" or "This commit" in the commit message. It is tautologically useless. Also, do $ git grep 'This patch' Documentation/process for more details. > does just that. > > Enablement is restricted to all machines advertising IRPERF capability, > except those susceptible to an erratum that makes the IRPERF return > bad values. > > That erratum occurs in Family 17h models 00-1fh [1], but not in F17h > models 20h and above [2]. > > AFTER (on a family 17h model 31h machine): > > $ sudo perf stat -e instructions,msr/irperf/ true > > Performance counter stats for 'true': > > 621,690 instructions > # 0.00 stalled cycles per insn > 622,490 msr/irperf/ > > [1] "Revision Guide for AMD Family 17h Models 00h-0Fh Processors", > currently available here: > > https://www.amd.com/system/files/TechDocs/55449_Fam_17h_M_00h-0Fh_Rev_Guide.pdf > > [2] "Revision Guide for AMD Family 17h Models 30h-3Fh Processors", > currently available here: > > https://developer.amd.com/wp-content/resources/56323-PUB_0.74.pdf How stable are those links? Past experience shows not very. Please upload those to a bugzilla.kernel.org entry and add that URL here with a Link: tag. > Cc: Alexander Shishkin > Cc: Andi Kleen > Cc: Arnaldo Carvalho de Melo > Cc: Babu Moger > Cc: Borislav Petkov > Cc: Fenghua Yu > Cc: Frank van der Linden > Cc: H. Peter Anvin > Cc: Huang Rui > Cc: Ingo Molnar > Cc: Ingo Molnar > Cc: Janakarajan Natarajan > Cc: Jan Beulich > Cc: Jiaxun Yang > Cc: Jiri Olsa > Cc: Josh Poimboeuf > Cc: Linus Torvalds > Cc: Luwei Kang > Cc: Martin Liška > Cc: Matt Fleming > Cc: Michael Petlan > Cc: Namhyung Kim > Cc: Paolo Bonzini > Cc: Pawan Gupta > Cc: Peter Zijlstra > Cc: Suravee Suthikulpanit > Cc: Thomas Gleixner > Cc: Tom Lendacky > Cc: x86@kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: stable@vger.kernel.org > Fixes: aaf248848db50 ("perf/x86/msr: Add AMD IRPERF (Instructions Retired) performance counter") > Signed-off-by: Kim Phillips > --- > RESEND, adding Michael Petlan to cc. Original v2: > > https://lore.kernel.org/lkml/20200121171232.28839-2-kim.phillips@amd.com/ > > v2: Based on Andi Kleen's review: > > https://lore.kernel.org/lkml/20200116040324.GI302770@tassilo.jf.intel.com/ > > Add an amd_erratum_1054 and use cpu_has_bug infrastructure instead of > open-coding the {family,model} check. > > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/include/asm/msr-index.h | 2 ++ > arch/x86/kernel/cpu/amd.c | 17 +++++++++++++++++ > 3 files changed, 20 insertions(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index f3327cb56edf..1c1600e7476b 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -404,5 +404,6 @@ > #define X86_BUG_SWAPGS X86_BUG(21) /* CPU is affected by speculation through SWAPGS */ > #define X86_BUG_TAA X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */ > #define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */ > +#define X86_BUG_AMD_E1054 X86_BUG(24) /* CPU is among the affected by Erratum 1054 */ That is visible in /proc/cpuinfo and the string "amd_e1054" means nothing. Call that X86_BUG_IRPERF or so to at least give some hint as to what the bug is. > > #endif /* _ASM_X86_CPUFEATURES_H */ > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index ebe1685e92dd..d5e517d1c3dd 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -512,6 +512,8 @@ > #define MSR_K7_HWCR 0xc0010015 > #define MSR_K7_HWCR_SMMLOCK_BIT 0 > #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) > +#define MSR_K7_HWCR_IRPERF_EN_BIT 30 > +#define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) > #define MSR_K7_FID_VID_CTL 0xc0010041 > #define MSR_K7_FID_VID_STATUS 0xc0010042 > > diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c > index 62c30279be77..c067234a271f 100644 > --- a/arch/x86/kernel/cpu/amd.c > +++ b/arch/x86/kernel/cpu/amd.c > @@ -28,6 +28,7 @@ > > static const int amd_erratum_383[]; > static const int amd_erratum_400[]; > +static const int amd_erratum_1054[]; > static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); > > /* > @@ -701,6 +702,9 @@ static void early_init_amd(struct cpuinfo_x86 *c) > if (cpu_has_amd_erratum(c, amd_erratum_400)) > set_cpu_bug(c, X86_BUG_AMD_E400); > > + if (cpu_has_amd_erratum(c, amd_erratum_1054)) > + set_cpu_bug(c, X86_BUG_AMD_E1054); > + > early_detect_mem_encrypt(c); > > /* Re-enable TopologyExtensions if switched off by BIOS */ > @@ -978,6 +982,15 @@ static void init_amd(struct cpuinfo_x86 *c) > /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ > if (!cpu_has(c, X86_FEATURE_XENPV)) > set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); > + > + /* > + * Turn on the Instructions Retired free counter on machines not > + * susceptible to erratum #1054 "Instructions Retired Performance > + * Counter May Be Inaccurate" . ^ |--- fullstop. Thx. -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette