From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38914C3F2D7 for ; Tue, 3 Mar 2020 18:13:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 06A1A20656 for ; Tue, 3 Mar 2020 18:13:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1583259212; bh=OqbTCx4juC17gkZ8FMJ4QVdYKQ0vilFA0YrhvR7L0h4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=Vr9PGtVX3bYwErPIswOWIKlMEs0CwTh8o4fMF2fgOuPlaWDv9KnB/cvb/gcil39JL +hBrHm4UPFqB0cBWMiSOG0V5IZWogghLh+MAXMXjWtJZeCMaiizhyS8j0AXfK+jBfn 1WmPh+qh8hvTH7JVfcxoS0qkAVUwDPJGGJo7Adfo= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731100AbgCCRqR (ORCPT ); Tue, 3 Mar 2020 12:46:17 -0500 Received: from mail.kernel.org ([198.145.29.99]:52786 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731094AbgCCRqQ (ORCPT ); Tue, 3 Mar 2020 12:46:16 -0500 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 51585214DB; Tue, 3 Mar 2020 17:46:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1583257575; bh=OqbTCx4juC17gkZ8FMJ4QVdYKQ0vilFA0YrhvR7L0h4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=yV1S46nx3FHnL/ksbKKuvp5nRglMJCzW7VEpG1gQknbVmhsFdJVsW7qY+98TxhnP+ E4rcG8vAefaoYVGKHnPddT0vEBwPeSbwq5dB2mKhlWmlIuJA23kzStKmntJe9k8Xc5 p1d4ch7jrfr9H8XRSxT3XRzX1bWAtgqNGIVAjrBQ= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Yongqiang Sun , Eric Yang , Bhawanpreet Lakha , Alex Deucher , Sasha Levin Subject: [PATCH 5.5 048/176] drm/amd/display: Limit minimum DPPCLK to 100MHz. Date: Tue, 3 Mar 2020 18:41:52 +0100 Message-Id: <20200303174310.110563013@linuxfoundation.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200303174304.593872177@linuxfoundation.org> References: <20200303174304.593872177@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Yongqiang Sun [ Upstream commit 6c81917a0485ee2a1be0dc23321ac10ecfd9578b ] [Why] Underflow is observed when plug in a 4K@60 monitor with 1366x768 eDP due to DPPCLK is too low. [How] Limit minimum DPPCLK to 100MHz. Signed-off-by: Yongqiang Sun Reviewed-by: Eric Yang Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index dbf063856846e..5f683d118d2aa 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -149,6 +149,12 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base, rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); } + // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. + if (!IS_DIAG_DC(dc->ctx->dce_environment)) { + if (new_clocks->dppclk_khz < 100000) + new_clocks->dppclk_khz = 100000; + } + if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) dpp_clock_lowered = true; -- 2.20.1