From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1888FC18E5B for ; Mon, 16 Mar 2020 02:39:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D5864205C9 for ; Mon, 16 Mar 2020 02:39:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584326360; bh=OVFFe6LVDT1McSdceRcLJ0lU84O4es66sWRpFFWGBb4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=NIETK5dNyHIMXX81EU5irMZh2rFQovlXo+gSVceaipc4rz9pKsfmmB9mtdQcwYjnF /Ep30JRG7YCsFxzALk6uXeNM2t2/mouATZ+nZ1Iq/UaBw3YJRXrqdbPVn9oaFlOz/H UHIklEr4YmPW5w1j/yooUX8zhT7BWsh4CkHYJ00U= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730114AbgCPCjH (ORCPT ); Sun, 15 Mar 2020 22:39:07 -0400 Received: from mail.kernel.org ([198.145.29.99]:38156 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729475AbgCPCee (ORCPT ); Sun, 15 Mar 2020 22:34:34 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 588D0206EB; Mon, 16 Mar 2020 02:34:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584326074; bh=OVFFe6LVDT1McSdceRcLJ0lU84O4es66sWRpFFWGBb4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jzY3E/0WLgYZ5iuIFyab7l8SRnR2OHQfTgDWbPHRbWowLapwXulGsjPyXZOWbR10r GhHROs9t4KROcfu94BqSxd5aivTCyFF5LWBovUKUkj+glT2q/RF6WgtN2Eog/YTJDF +jEa350ptKPYQhF38vJI2Xg6p05KAAjYDd6YZD/g= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Joakim Zhang , Will Deacon , Sasha Levin , linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 5.4 19/35] drivers/perf: fsl_imx8_ddr: Correct the CLEAR bit definition Date: Sun, 15 Mar 2020 22:33:55 -0400 Message-Id: <20200316023411.1263-19-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200316023411.1263-1-sashal@kernel.org> References: <20200316023411.1263-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Joakim Zhang [ Upstream commit 049d919168458ac54e7fad27cd156a958b042d2f ] When disabling a counter from ddr_perf_event_stop(), the counter value is reset to 0 at the same time. Preserve the counter value by performing a read-modify-write of the PMU register and clearing only the enable bit. Signed-off-by: Joakim Zhang Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- drivers/perf/fsl_imx8_ddr_perf.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 0e51baa48b149..6eef47de8fccc 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -327,9 +327,10 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, if (enable) { /* - * must disable first, then enable again - * otherwise, cycle counter will not work - * if previous state is enabled. + * cycle counter is special which should firstly write 0 then + * write 1 into CLEAR bit to clear it. Other counters only + * need write 0 into CLEAR bit and it turns out to be 1 by + * hardware. Below enable flow is harmless for all counters. */ writel(0, pmu->base + reg); val = CNTL_EN | CNTL_CLEAR; @@ -337,7 +338,8 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, writel(val, pmu->base + reg); } else { /* Disable counter */ - writel(0, pmu->base + reg); + val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK; + writel(val, pmu->base + reg); } } -- 2.20.1