[v5.5] Fix up eSDHC issue on P2020

[v5.5] Fix up eSDHC issue on P2020

[Yangbo Lu]

The upstream commit broke P2020 eSDHC.
fe0acab mmc: sdhci-of-esdhc: fix P2020 errata handling

While the issue was fixed by later commit.
2aa3d82 mmc: sdhci-of-esdhc: fix esdhc_reset() for different controller versions

The commit fe0acab had been applied to stable kernel 5.5, 5.4,
4.19, 4.14, 4.9, and 4.4 without that fix-up.

To fix up P2020 eSDHC on the stable kernels, backport the fix-up 2aa3d82
kernel 5.4 and 5.5.

Please help to revert fe0acab on 4.19, 4.14, 4.9 and 4.4, since there are
many conflicts to cherry-pick the fix-up, and fe0acab is actually not strongly
required for handling errata which is hardly triggered.

The email thread for the issue discussion.
https://www.spinics.net/lists/stable/msg375823.html

Yangbo Lu (4):
  mmc: sdhci-of-esdhc: fix esdhc_reset() for different controller
    versions
  mmc: sdhci-of-esdhc: fix clock setting for different controller
    versions
  mmc: sdhci-of-esdhc: fix transfer mode register reading
  mmc: sdhci-of-esdhc: fix serious issue clock is always disabled

 drivers/mmc/host/sdhci-of-esdhc.c | 174 +++++++++++++++++++++++++-------------
 1 file changed, 114 insertions(+), 60 deletions(-)

-- 
2.7.4

[v5.5] mmc: sdhci-of-esdhc: fix esdhc_reset() for different controller versions

[Yangbo Lu]

commit 2aa3d826adb578b26629a79b775a552cfe3fedf7 upstream.

This patch is to fix operating in esdhc_reset() for different
controller versions, and to add bus-width restoring after data
reset for eSDHC (verdor version <= 2.2).

Also add annotation for understanding.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20200108040713.38888-1-yangbo.lu@nxp.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
---
 drivers/mmc/host/sdhci-of-esdhc.c | 43 +++++++++++++++++++++++++++++++++++----
 1 file changed, 39 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index fcfb50f..fd1251e 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -734,23 +734,58 @@ static void esdhc_reset(struct sdhci_host *host, u8 mask)
 {
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
-	u32 val;
+	u32 val, bus_width = 0;
 
+	/*
+	 * Add delay to make sure all the DMA transfers are finished
+	 * for quirk.
+	 */
 	if (esdhc->quirk_delay_before_data_reset &&
 	    (mask & SDHCI_RESET_DATA) &&
 	    (host->flags & SDHCI_REQ_USE_DMA))
 		mdelay(5);
 
+	/*
+	 * Save bus-width for eSDHC whose vendor version is 2.2
+	 * or lower for data reset.
+	 */
+	if ((mask & SDHCI_RESET_DATA) &&
+	    (esdhc->vendor_ver <= VENDOR_V_22)) {
+		val = sdhci_readl(host, ESDHC_PROCTL);
+		bus_width = val & ESDHC_CTRL_BUSWIDTH_MASK;
+	}
+
 	sdhci_reset(host, mask);
 
-	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
-	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+	/*
+	 * Restore bus-width setting and interrupt registers for eSDHC
+	 * whose vendor version is 2.2 or lower for data reset.
+	 */
+	if ((mask & SDHCI_RESET_DATA) &&
+	    (esdhc->vendor_ver <= VENDOR_V_22)) {
+		val = sdhci_readl(host, ESDHC_PROCTL);
+		val &= ~ESDHC_CTRL_BUSWIDTH_MASK;
+		val |= bus_width;
+		sdhci_writel(host, val, ESDHC_PROCTL);
+
+		sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+		sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+	}
 
-	if (mask & SDHCI_RESET_ALL) {
+	/*
+	 * Some bits have to be cleaned manually for eSDHC whose spec
+	 * version is higher than 3.0 for all reset.
+	 */
+	if ((mask & SDHCI_RESET_ALL) &&
+	    (esdhc->spec_ver >= SDHCI_SPEC_300)) {
 		val = sdhci_readl(host, ESDHC_TBCTL);
 		val &= ~ESDHC_TB_EN;
 		sdhci_writel(host, val, ESDHC_TBCTL);
 
+		/*
+		 * Initialize eSDHC_DLLCFG1[DLL_PD_PULSE_STRETCH_SEL] to
+		 * 0 for quirk.
+		 */
 		if (esdhc->quirk_unreliable_pulse_detection) {
 			val = sdhci_readl(host, ESDHC_DLLCFG1);
 			val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL;
-- 
2.7.4

RE: [v5.5] Fix up eSDHC issue on P2020

[Y.b. Lu]

> -----Original Message-----
> From: Yangbo Lu <yangbo.lu@nxp.com>
> Sent: Wednesday, April 15, 2020 11:52 AM
> To: stable@vger.kernel.org
> Cc: Y.b. Lu <yangbo.lu@nxp.com>; Greg Kroah-Hartman
> <gregkh@linuxfoundation.org>; Sasha Levin <sashal@kernel.org>; Daniel
> Walker <danielwa@cisco.com>; Ulf Hansson <ulf.hansson@linaro.org>
> Subject: [v5.5] Fix up eSDHC issue on P2020
> 
> The upstream commit broke P2020 eSDHC.
> fe0acab mmc: sdhci-of-esdhc: fix P2020 errata handling
> 
> While the issue was fixed by later commit.
> 2aa3d82 mmc: sdhci-of-esdhc: fix esdhc_reset() for different controller
> versions
> 
> The commit fe0acab had been applied to stable kernel 5.5, 5.4,
> 4.19, 4.14, 4.9, and 4.4 without that fix-up.
> 
> To fix up P2020 eSDHC on the stable kernels, backport the fix-up 2aa3d82
> kernel 5.4 and 5.5.
> 
> Please help to revert fe0acab on 4.19, 4.14, 4.9 and 4.4, since there are
> many conflicts to cherry-pick the fix-up, and fe0acab is actually not strongly
> required for handling errata which is hardly triggered.
> 
> The email thread for the issue discussion.
> https://www.spinics.net/lists/stable/msg375823.html
> 
> Yangbo Lu (4):
>   mmc: sdhci-of-esdhc: fix esdhc_reset() for different controller
>     versions
>   mmc: sdhci-of-esdhc: fix clock setting for different controller
>     versions
>   mmc: sdhci-of-esdhc: fix transfer mode register reading
>   mmc: sdhci-of-esdhc: fix serious issue clock is always disabled
> 
>  drivers/mmc/host/sdhci-of-esdhc.c | 174
> +++++++++++++++++++++++++-------------
>  1 file changed, 114 insertions(+), 60 deletions(-)

Sorry, please ignore the wrong patch list and changes here in cover letter.
It is to backport only fix-up 2aa3d82.

> 
> --
> 2.7.4

Re: [v5.5] mmc: sdhci-of-esdhc: fix esdhc_reset() for different controller versions

[Greg Kroah-Hartman]

On Wed, Apr 15, 2020 at 11:52:12AM +0800, Yangbo Lu wrote:
> commit 2aa3d826adb578b26629a79b775a552cfe3fedf7 upstream.
> 
> This patch is to fix operating in esdhc_reset() for different
> controller versions, and to add bus-width restoring after data
> reset for eSDHC (verdor version <= 2.2).
> 
> Also add annotation for understanding.
> 
> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> Link: https://lore.kernel.org/r/20200108040713.38888-1-yangbo.lu@nxp.com
> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
> ---
>  drivers/mmc/host/sdhci-of-esdhc.c | 43 +++++++++++++++++++++++++++++++++++----
>  1 file changed, 39 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
> index fcfb50f..fd1251e 100644
> --- a/drivers/mmc/host/sdhci-of-esdhc.c
> +++ b/drivers/mmc/host/sdhci-of-esdhc.c
> @@ -734,23 +734,58 @@ static void esdhc_reset(struct sdhci_host *host, u8 mask)
>  {
>  	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>  	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
> -	u32 val;
> +	u32 val, bus_width = 0;
>  
> +	/*
> +	 * Add delay to make sure all the DMA transfers are finished
> +	 * for quirk.
> +	 */
>  	if (esdhc->quirk_delay_before_data_reset &&
>  	    (mask & SDHCI_RESET_DATA) &&
>  	    (host->flags & SDHCI_REQ_USE_DMA))
>  		mdelay(5);
>  
> +	/*
> +	 * Save bus-width for eSDHC whose vendor version is 2.2
> +	 * or lower for data reset.
> +	 */
> +	if ((mask & SDHCI_RESET_DATA) &&
> +	    (esdhc->vendor_ver <= VENDOR_V_22)) {
> +		val = sdhci_readl(host, ESDHC_PROCTL);
> +		bus_width = val & ESDHC_CTRL_BUSWIDTH_MASK;
> +	}
> +
>  	sdhci_reset(host, mask);
>  
> -	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
> -	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
> +	/*
> +	 * Restore bus-width setting and interrupt registers for eSDHC
> +	 * whose vendor version is 2.2 or lower for data reset.
> +	 */
> +	if ((mask & SDHCI_RESET_DATA) &&
> +	    (esdhc->vendor_ver <= VENDOR_V_22)) {
> +		val = sdhci_readl(host, ESDHC_PROCTL);
> +		val &= ~ESDHC_CTRL_BUSWIDTH_MASK;
> +		val |= bus_width;
> +		sdhci_writel(host, val, ESDHC_PROCTL);
> +
> +		sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
> +		sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
> +	}
>  
> -	if (mask & SDHCI_RESET_ALL) {
> +	/*
> +	 * Some bits have to be cleaned manually for eSDHC whose spec
> +	 * version is higher than 3.0 for all reset.
> +	 */
> +	if ((mask & SDHCI_RESET_ALL) &&
> +	    (esdhc->spec_ver >= SDHCI_SPEC_300)) {
>  		val = sdhci_readl(host, ESDHC_TBCTL);
>  		val &= ~ESDHC_TB_EN;
>  		sdhci_writel(host, val, ESDHC_TBCTL);
>  
> +		/*
> +		 * Initialize eSDHC_DLLCFG1[DLL_PD_PULSE_STRETCH_SEL] to
> +		 * 0 for quirk.
> +		 */
>  		if (esdhc->quirk_unreliable_pulse_detection) {
>  			val = sdhci_readl(host, ESDHC_DLLCFG1);
>  			val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL;
> -- 
> 2.7.4
> 

Now applied to 5.5.y and 5.4.y, thanks.

greg k-h