* [PATCH] drm/i915/gt: Update PMINTRMSK holding fw
@ 2020-04-15 7:50 Chris Wilson
2020-04-15 11:09 ` Mika Kuoppala
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Chris Wilson @ 2020-04-15 7:50 UTC (permalink / raw)
To: intel-gfx
Cc: Chris Wilson, Francisco Jerez, Mika Kuoppala, Andi Shyti, stable
If we use a non-forcewaked write to PMINTRMSK, it does not take effect
until much later, if at all, causing a loss of RPS interrupts and no GPU
reclocking, leaving the GPU running at the wrong frequency for long
periods of time.
Reported-by: Francisco Jerez <currojerez@riseup.net>
Suggested-by: Francisco Jerez <currojerez@riseup.net>
Fixes: 35cc7f32c298 ("drm/i915/gt: Use non-forcewake writes for RPS")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Francisco Jerez <currojerez@riseup.net>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Cc: <stable@vger.kernel.org> # v5.6+
---
drivers/gpu/drm/i915/gt/intel_rps.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 86110458e2a7..6a3505467406 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -81,13 +81,14 @@ static void rps_enable_interrupts(struct intel_rps *rps)
events = (GEN6_PM_RP_UP_THRESHOLD |
GEN6_PM_RP_DOWN_THRESHOLD |
GEN6_PM_RP_DOWN_TIMEOUT);
-
WRITE_ONCE(rps->pm_events, events);
+
spin_lock_irq(>->irq_lock);
gen6_gt_pm_enable_irq(gt, rps->pm_events);
spin_unlock_irq(>->irq_lock);
- set(gt->uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, rps->cur_freq));
+ intel_uncore_write(gt->uncore,
+ GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));
}
static void gen6_rps_reset_interrupts(struct intel_rps *rps)
@@ -120,7 +121,9 @@ static void rps_disable_interrupts(struct intel_rps *rps)
struct intel_gt *gt = rps_to_gt(rps);
WRITE_ONCE(rps->pm_events, 0);
- set(gt->uncore, GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
+
+ intel_uncore_write(gt->uncore,
+ GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
spin_lock_irq(>->irq_lock);
gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);
--
2.20.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915/gt: Update PMINTRMSK holding fw
2020-04-15 7:50 [PATCH] drm/i915/gt: Update PMINTRMSK holding fw Chris Wilson
@ 2020-04-15 11:09 ` Mika Kuoppala
2020-04-15 11:24 ` Andi Shyti
2020-04-15 19:14 ` Francisco Jerez
2 siblings, 0 replies; 5+ messages in thread
From: Mika Kuoppala @ 2020-04-15 11:09 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson, Francisco Jerez, Andi Shyti, stable
Chris Wilson <chris@chris-wilson.co.uk> writes:
> If we use a non-forcewaked write to PMINTRMSK, it does not take effect
> until much later, if at all, causing a loss of RPS interrupts and no GPU
> reclocking, leaving the GPU running at the wrong frequency for long
> periods of time.
>
> Reported-by: Francisco Jerez <currojerez@riseup.net>
> Suggested-by: Francisco Jerez <currojerez@riseup.net>
> Fixes: 35cc7f32c298 ("drm/i915/gt: Use non-forcewake writes for RPS")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Francisco Jerez <currojerez@riseup.net>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> Cc: <stable@vger.kernel.org> # v5.6+
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 86110458e2a7..6a3505467406 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -81,13 +81,14 @@ static void rps_enable_interrupts(struct intel_rps *rps)
> events = (GEN6_PM_RP_UP_THRESHOLD |
> GEN6_PM_RP_DOWN_THRESHOLD |
> GEN6_PM_RP_DOWN_TIMEOUT);
> -
> WRITE_ONCE(rps->pm_events, events);
> +
> spin_lock_irq(>->irq_lock);
> gen6_gt_pm_enable_irq(gt, rps->pm_events);
> spin_unlock_irq(>->irq_lock);
>
> - set(gt->uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, rps->cur_freq));
> + intel_uncore_write(gt->uncore,
> + GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));
> }
>
> static void gen6_rps_reset_interrupts(struct intel_rps *rps)
> @@ -120,7 +121,9 @@ static void rps_disable_interrupts(struct intel_rps *rps)
> struct intel_gt *gt = rps_to_gt(rps);
>
> WRITE_ONCE(rps->pm_events, 0);
> - set(gt->uncore, GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
> +
> + intel_uncore_write(gt->uncore,
> + GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
>
> spin_lock_irq(>->irq_lock);
> gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);
> --
> 2.20.1
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915/gt: Update PMINTRMSK holding fw
2020-04-15 7:50 [PATCH] drm/i915/gt: Update PMINTRMSK holding fw Chris Wilson
2020-04-15 11:09 ` Mika Kuoppala
@ 2020-04-15 11:24 ` Andi Shyti
2020-04-15 19:14 ` Francisco Jerez
2 siblings, 0 replies; 5+ messages in thread
From: Andi Shyti @ 2020-04-15 11:24 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, Francisco Jerez, Mika Kuoppala, stable
Hi Chris,
On Wed, Apr 15, 2020 at 08:50:18AM +0100, Chris Wilson wrote:
> If we use a non-forcewaked write to PMINTRMSK, it does not take effect
> until much later, if at all, causing a loss of RPS interrupts and no GPU
> reclocking, leaving the GPU running at the wrong frequency for long
> periods of time.
>
> Reported-by: Francisco Jerez <currojerez@riseup.net>
> Suggested-by: Francisco Jerez <currojerez@riseup.net>
> Fixes: 35cc7f32c298 ("drm/i915/gt: Use non-forcewake writes for RPS")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Francisco Jerez <currojerez@riseup.net>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> Cc: <stable@vger.kernel.org> # v5.6+
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Andi
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915/gt: Update PMINTRMSK holding fw
2020-04-15 7:50 [PATCH] drm/i915/gt: Update PMINTRMSK holding fw Chris Wilson
2020-04-15 11:09 ` Mika Kuoppala
2020-04-15 11:24 ` Andi Shyti
@ 2020-04-15 19:14 ` Francisco Jerez
2 siblings, 0 replies; 5+ messages in thread
From: Francisco Jerez @ 2020-04-15 19:14 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson, Mika Kuoppala, Andi Shyti, stable
[-- Attachment #1.1: Type: text/plain, Size: 2218 bytes --]
Chris Wilson <chris@chris-wilson.co.uk> writes:
> If we use a non-forcewaked write to PMINTRMSK, it does not take effect
> until much later, if at all, causing a loss of RPS interrupts and no GPU
> reclocking, leaving the GPU running at the wrong frequency for long
> periods of time.
>
> Reported-by: Francisco Jerez <currojerez@riseup.net>
> Suggested-by: Francisco Jerez <currojerez@riseup.net>
> Fixes: 35cc7f32c298 ("drm/i915/gt: Use non-forcewake writes for RPS")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
> Cc: Francisco Jerez <currojerez@riseup.net>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> Cc: <stable@vger.kernel.org> # v5.6+
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 86110458e2a7..6a3505467406 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -81,13 +81,14 @@ static void rps_enable_interrupts(struct intel_rps *rps)
> events = (GEN6_PM_RP_UP_THRESHOLD |
> GEN6_PM_RP_DOWN_THRESHOLD |
> GEN6_PM_RP_DOWN_TIMEOUT);
> -
> WRITE_ONCE(rps->pm_events, events);
> +
> spin_lock_irq(>->irq_lock);
> gen6_gt_pm_enable_irq(gt, rps->pm_events);
> spin_unlock_irq(>->irq_lock);
>
> - set(gt->uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, rps->cur_freq));
> + intel_uncore_write(gt->uncore,
> + GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));
> }
>
> static void gen6_rps_reset_interrupts(struct intel_rps *rps)
> @@ -120,7 +121,9 @@ static void rps_disable_interrupts(struct intel_rps *rps)
> struct intel_gt *gt = rps_to_gt(rps);
>
> WRITE_ONCE(rps->pm_events, 0);
> - set(gt->uncore, GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
> +
> + intel_uncore_write(gt->uncore,
> + GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
>
> spin_lock_irq(>->irq_lock);
> gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);
> --
> 2.20.1
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] drm/i915/gt: Update PMINTRMSK holding fw
@ 2020-04-27 20:26 Chris Wilson
0 siblings, 0 replies; 5+ messages in thread
From: Chris Wilson @ 2020-04-27 20:26 UTC (permalink / raw)
To: stable
Cc: Chris Wilson, Francisco Jerez, Mika Kuoppala, Andi Shyti,
Rodrigo Vivi
Upstream commit e1eb075c5051987fbbadbc0fb8211679df657721.
If we use a non-forcewaked write to PMINTRMSK, it does not take effect
until much later, if at all, causing a loss of RPS interrupts and no GPU
reclocking, leaving the GPU running at the wrong frequency for long
periods of time.
Reported-by: Francisco Jerez <currojerez@riseup.net>
Suggested-by: Francisco Jerez <currojerez@riseup.net>
Fixes: 35cc7f32c298 ("drm/i915/gt: Use non-forcewake writes for RPS")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Francisco Jerez <currojerez@riseup.net>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Cc: <stable@vger.kernel.org> # v5.6+
Link: https://patchwork.freedesktop.org/patch/msgid/20200415170318.16771-2-chris@chris-wilson.co.uk
(cherry picked from commit a080bd994c4023042a2b605c65fa10a25933f636)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
(cherry picked from commit e1eb075c5051987fbbadbc0fb8211679df657721)
---
drivers/gpu/drm/i915/gt/intel_rps.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index b2d245963d9f..8accea06185b 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -83,7 +83,8 @@ static void rps_enable_interrupts(struct intel_rps *rps)
gen6_gt_pm_enable_irq(gt, rps->pm_events);
spin_unlock_irq(>->irq_lock);
- set(gt->uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, rps->cur_freq));
+ intel_uncore_write(gt->uncore,
+ GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));
}
static void gen6_rps_reset_interrupts(struct intel_rps *rps)
@@ -117,7 +118,8 @@ static void rps_disable_interrupts(struct intel_rps *rps)
rps->pm_events = 0;
- set(gt->uncore, GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
+ intel_uncore_write(gt->uncore,
+ GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
spin_lock_irq(>->irq_lock);
gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);
--
2.26.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
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2020-04-15 7:50 [PATCH] drm/i915/gt: Update PMINTRMSK holding fw Chris Wilson
2020-04-15 11:09 ` Mika Kuoppala
2020-04-15 11:24 ` Andi Shyti
2020-04-15 19:14 ` Francisco Jerez
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2020-04-27 20:26 Chris Wilson
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