* [PATCH v3 01/11] PCI: qcom: add missing ipq806x clocks in PCIe driver
[not found] <20200430220619.3169-1-ansuelsmth@gmail.com>
@ 2020-04-30 22:06 ` Ansuel Smith
2020-05-06 23:42 ` Sasha Levin
` (2 more replies)
2020-04-30 22:06 ` [PATCH v3 04/11] PCI: qcom: add missing reset for ipq806x Ansuel Smith
2020-04-30 22:06 ` [PATCH v3 07/11] PCI: qcom: add support for defining some PARF params Ansuel Smith
2 siblings, 3 replies; 8+ messages in thread
From: Ansuel Smith @ 2020-04-30 22:06 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ansuel Smith, Sham Muthayyan, stable, Andy Gross, Bjorn Helgaas,
Rob Herring, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
Aux and Ref clk are missing in PCIe qcom driver.
Add support in the driver to fix PCIe initialization in ipq806x.
Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v4.5+
---
drivers/pci/controller/dwc/pcie-qcom.c | 44 ++++++++++++++++++++++----
1 file changed, 38 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 5ea527a6bd9f..2a39dfdccfc8 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 {
struct clk *iface_clk;
struct clk *core_clk;
struct clk *phy_clk;
+ struct clk *aux_clk;
+ struct clk *ref_clk;
struct reset_control *pci_reset;
struct reset_control *axi_reset;
struct reset_control *ahb_reset;
@@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
if (IS_ERR(res->phy_clk))
return PTR_ERR(res->phy_clk);
+ res->aux_clk = devm_clk_get_optional(dev, "aux");
+ if (IS_ERR(res->aux_clk))
+ return PTR_ERR(res->aux_clk);
+
+ res->ref_clk = devm_clk_get_optional(dev, "ref");
+ if (IS_ERR(res->ref_clk))
+ return PTR_ERR(res->ref_clk);
+
res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
if (IS_ERR(res->pci_reset))
return PTR_ERR(res->pci_reset);
@@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
clk_disable_unprepare(res->phy_clk);
+ clk_disable_unprepare(res->aux_clk);
+ clk_disable_unprepare(res->ref_clk);
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
}
@@ -307,16 +319,32 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_assert_ahb;
}
+ ret = clk_prepare_enable(res->core_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable core clock\n");
+ goto err_clk_core;
+ }
+
ret = clk_prepare_enable(res->phy_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable phy clock\n");
goto err_clk_phy;
}
- ret = clk_prepare_enable(res->core_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable core clock\n");
- goto err_clk_core;
+ if (res->aux_clk) {
+ ret = clk_prepare_enable(res->aux_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable aux clock\n");
+ goto err_clk_aux;
+ }
+ }
+
+ if (res->ref_clk) {
+ ret = clk_prepare_enable(res->ref_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable ref clock\n");
+ goto err_clk_ref;
+ }
}
ret = reset_control_deassert(res->ahb_reset);
@@ -372,10 +400,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
return 0;
err_deassert_ahb:
- clk_disable_unprepare(res->core_clk);
-err_clk_core:
+ clk_disable_unprepare(res->ref_clk);
+err_clk_ref:
+ clk_disable_unprepare(res->aux_clk);
+err_clk_aux:
clk_disable_unprepare(res->phy_clk);
err_clk_phy:
+ clk_disable_unprepare(res->core_clk);
+err_clk_core:
clk_disable_unprepare(res->iface_clk);
err_assert_ahb:
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v3 01/11] PCI: qcom: add missing ipq806x clocks in PCIe driver
2020-04-30 22:06 ` [PATCH v3 01/11] PCI: qcom: add missing ipq806x clocks in PCIe driver Ansuel Smith
@ 2020-05-06 23:42 ` Sasha Levin
2020-05-07 17:54 ` Rob Herring
2020-05-08 11:51 ` Stanimir Varbanov
2 siblings, 0 replies; 8+ messages in thread
From: Sasha Levin @ 2020-05-06 23:42 UTC (permalink / raw)
To: Sasha Levin, Ansuel Smith, Bjorn Andersson; +Cc: Ansuel Smith, stable
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 1890 bytes --]
Hi
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag
fixing commit: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver").
The bot has tested the following trees: v5.6.8, v5.4.36, v4.19.119, v4.14.177, v4.9.220.
v5.6.8: Build OK!
v5.4.36: Build OK!
v4.19.119: Build failed! Errors:
drivers/pci/controller/dwc/pcie-qcom.c:240:17: error: implicit declaration of function ‘devm_clk_get_optional’; did you mean ‘devm_gpiod_get_optional’? [-Werror=implicit-function-declaration]
v4.14.177: Failed to apply! Possible dependencies:
68e7c15ceb8d ("PCI: qcom: Use regulator bulk api for apq8064 supplies")
v4.9.220: Failed to apply! Possible dependencies:
11a61a860281 ("PCI: dwc: Use PTR_ERR_OR_ZERO to simplify code")
19ce01cc8cbc ("PCI: dwc: all: Rename cfg_read/cfg_write to read/write")
1d77040bde2d ("PCI: layerscape: Add LS1046a support")
1f6c4501c667 ("PCI: dra7xx: Group PHY API invocations")
244e00071fd8 ("PCI: qcom: Explicitly request exclusive reset control")
40f67fb2c384 ("PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init()")
442ec4c04d12 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures")
5d0f1b84c526 ("PCI: qcom: Reorder to put v0 functions together, v1 functions together, etc")
9bcf0a6fdc50 ("PCI: dwc: all: Use platform_set_drvdata() to save private data")
ab5fe4f4d31e ("PCI: dra7xx: Add support to force RC to work in GEN1 mode")
d0491fc39bdd ("PCI: qcom: Add support for MSM8996 PCIe controller")
e594233803aa ("PCI: layerscape: Remove redundant error message from ls_pcie_probe()")
ebe85a44aad4 ("PCI: dra7xx: Enable MSI and legacy interrupts simultaneously")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v3 01/11] PCI: qcom: add missing ipq806x clocks in PCIe driver
2020-04-30 22:06 ` [PATCH v3 01/11] PCI: qcom: add missing ipq806x clocks in PCIe driver Ansuel Smith
2020-05-06 23:42 ` Sasha Levin
@ 2020-05-07 17:54 ` Rob Herring
2020-05-08 11:51 ` Stanimir Varbanov
2 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2020-05-07 17:54 UTC (permalink / raw)
To: Ansuel Smith
Cc: Bjorn Andersson, Sham Muthayyan, stable, Andy Gross,
Bjorn Helgaas, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
On Fri, May 01, 2020 at 12:06:08AM +0200, Ansuel Smith wrote:
> Aux and Ref clk are missing in PCIe qcom driver.
> Add support in the driver to fix PCIe initialization in ipq806x.
>
> Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver
> Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Cc: stable@vger.kernel.org # v4.5+
Doesn't strike me as stable material. Looks like new h/w enablement.
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 44 ++++++++++++++++++++++----
> 1 file changed, 38 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 5ea527a6bd9f..2a39dfdccfc8 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 {
> struct clk *iface_clk;
> struct clk *core_clk;
> struct clk *phy_clk;
> + struct clk *aux_clk;
> + struct clk *ref_clk;
> struct reset_control *pci_reset;
> struct reset_control *axi_reset;
> struct reset_control *ahb_reset;
> @@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
> if (IS_ERR(res->phy_clk))
> return PTR_ERR(res->phy_clk);
>
> + res->aux_clk = devm_clk_get_optional(dev, "aux");
> + if (IS_ERR(res->aux_clk))
> + return PTR_ERR(res->aux_clk);
> +
> + res->ref_clk = devm_clk_get_optional(dev, "ref");
> + if (IS_ERR(res->ref_clk))
> + return PTR_ERR(res->ref_clk);
Seems like you'd want to report an error for ipq608x? Based on the
commit msg, they aren't optional.
> +
> res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
> if (IS_ERR(res->pci_reset))
> return PTR_ERR(res->pci_reset);
> @@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
> clk_disable_unprepare(res->iface_clk);
> clk_disable_unprepare(res->core_clk);
> clk_disable_unprepare(res->phy_clk);
> + clk_disable_unprepare(res->aux_clk);
> + clk_disable_unprepare(res->ref_clk);
> regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
> }
>
> @@ -307,16 +319,32 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
> goto err_assert_ahb;
> }
>
> + ret = clk_prepare_enable(res->core_clk);
Perhaps use the bulk api.
> + if (ret) {
> + dev_err(dev, "cannot prepare/enable core clock\n");
> + goto err_clk_core;
> + }
> +
> ret = clk_prepare_enable(res->phy_clk);
> if (ret) {
> dev_err(dev, "cannot prepare/enable phy clock\n");
> goto err_clk_phy;
> }
>
> - ret = clk_prepare_enable(res->core_clk);
> - if (ret) {
> - dev_err(dev, "cannot prepare/enable core clock\n");
> - goto err_clk_core;
> + if (res->aux_clk) {
> + ret = clk_prepare_enable(res->aux_clk);
> + if (ret) {
> + dev_err(dev, "cannot prepare/enable aux clock\n");
> + goto err_clk_aux;
> + }
> + }
> +
> + if (res->ref_clk) {
> + ret = clk_prepare_enable(res->ref_clk);
> + if (ret) {
> + dev_err(dev, "cannot prepare/enable ref clock\n");
> + goto err_clk_ref;
> + }
> }
>
> ret = reset_control_deassert(res->ahb_reset);
> @@ -372,10 +400,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
> return 0;
>
> err_deassert_ahb:
> - clk_disable_unprepare(res->core_clk);
> -err_clk_core:
> + clk_disable_unprepare(res->ref_clk);
> +err_clk_ref:
> + clk_disable_unprepare(res->aux_clk);
> +err_clk_aux:
> clk_disable_unprepare(res->phy_clk);
> err_clk_phy:
> + clk_disable_unprepare(res->core_clk);
> +err_clk_core:
> clk_disable_unprepare(res->iface_clk);
> err_assert_ahb:
> regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v3 01/11] PCI: qcom: add missing ipq806x clocks in PCIe driver
2020-04-30 22:06 ` [PATCH v3 01/11] PCI: qcom: add missing ipq806x clocks in PCIe driver Ansuel Smith
2020-05-06 23:42 ` Sasha Levin
2020-05-07 17:54 ` Rob Herring
@ 2020-05-08 11:51 ` Stanimir Varbanov
2 siblings, 0 replies; 8+ messages in thread
From: Stanimir Varbanov @ 2020-05-08 11:51 UTC (permalink / raw)
To: Ansuel Smith, Bjorn Andersson
Cc: Sham Muthayyan, stable, Andy Gross, Bjorn Helgaas, Rob Herring,
Mark Rutland, Lorenzo Pieralisi, Andrew Murray, Philipp Zabel,
linux-arm-msm, linux-pci, devicetree, linux-kernel
Hi Ansuel,
On 5/1/20 1:06 AM, Ansuel Smith wrote:
> Aux and Ref clk are missing in PCIe qcom driver.
> Add support in the driver to fix PCIe initialization in ipq806x.
>
> Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver
> Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Cc: stable@vger.kernel.org # v4.5+
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 44 ++++++++++++++++++++++----
> 1 file changed, 38 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 5ea527a6bd9f..2a39dfdccfc8 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 {
> struct clk *iface_clk;
> struct clk *core_clk;
> struct clk *phy_clk;
> + struct clk *aux_clk;
> + struct clk *ref_clk;
> struct reset_control *pci_reset;
> struct reset_control *axi_reset;
> struct reset_control *ahb_reset;
> @@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
> if (IS_ERR(res->phy_clk))
> return PTR_ERR(res->phy_clk);
>
> + res->aux_clk = devm_clk_get_optional(dev, "aux");
> + if (IS_ERR(res->aux_clk))
> + return PTR_ERR(res->aux_clk);
> +
> + res->ref_clk = devm_clk_get_optional(dev, "ref");
> + if (IS_ERR(res->ref_clk))
> + return PTR_ERR(res->ref_clk);
> +
> res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
> if (IS_ERR(res->pci_reset))
> return PTR_ERR(res->pci_reset);
> @@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
> clk_disable_unprepare(res->iface_clk);
> clk_disable_unprepare(res->core_clk);
> clk_disable_unprepare(res->phy_clk);
> + clk_disable_unprepare(res->aux_clk);
> + clk_disable_unprepare(res->ref_clk);
> regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
> }
>
> @@ -307,16 +319,32 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
> goto err_assert_ahb;
> }
>
> + ret = clk_prepare_enable(res->core_clk);
> + if (ret) {
> + dev_err(dev, "cannot prepare/enable core clock\n");
> + goto err_clk_core;
> + }
> +
> ret = clk_prepare_enable(res->phy_clk);
> if (ret) {
> dev_err(dev, "cannot prepare/enable phy clock\n");
> goto err_clk_phy;
> }
>
> - ret = clk_prepare_enable(res->core_clk);
> - if (ret) {
> - dev_err(dev, "cannot prepare/enable core clock\n");
> - goto err_clk_core;
> + if (res->aux_clk) {
you don't need this check, clk_prepare_enable handles NULL
> + ret = clk_prepare_enable(res->aux_clk);
> + if (ret) {
> + dev_err(dev, "cannot prepare/enable aux clock\n");
> + goto err_clk_aux;
> + }
> + }
> +
> + if (res->ref_clk) {
here too
> + ret = clk_prepare_enable(res->ref_clk);
> + if (ret) {
> + dev_err(dev, "cannot prepare/enable ref clock\n");
> + goto err_clk_ref;
> + }
> }
>
> ret = reset_control_deassert(res->ahb_reset);
> @@ -372,10 +400,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
> return 0;
>
> err_deassert_ahb:
> - clk_disable_unprepare(res->core_clk);
> -err_clk_core:
> + clk_disable_unprepare(res->ref_clk);
> +err_clk_ref:
> + clk_disable_unprepare(res->aux_clk);
> +err_clk_aux:
> clk_disable_unprepare(res->phy_clk);
> err_clk_phy:
> + clk_disable_unprepare(res->core_clk);
> +err_clk_core:
> clk_disable_unprepare(res->iface_clk);
> err_assert_ahb:
> regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
>
--
regards,
Stan
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 04/11] PCI: qcom: add missing reset for ipq806x
[not found] <20200430220619.3169-1-ansuelsmth@gmail.com>
2020-04-30 22:06 ` [PATCH v3 01/11] PCI: qcom: add missing ipq806x clocks in PCIe driver Ansuel Smith
@ 2020-04-30 22:06 ` Ansuel Smith
2020-05-07 18:00 ` Rob Herring
2020-05-08 7:20 ` Philipp Zabel
2020-04-30 22:06 ` [PATCH v3 07/11] PCI: qcom: add support for defining some PARF params Ansuel Smith
2 siblings, 2 replies; 8+ messages in thread
From: Ansuel Smith @ 2020-04-30 22:06 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ansuel Smith, Sham Muthayyan, stable, Andy Gross, Bjorn Helgaas,
Rob Herring, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
Add missing ext reset used by ipq8064 SoC in PCIe qcom driver.
Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v4.5+
---
drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 7a8901efc031..921030a64bab 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 {
struct reset_control *ahb_reset;
struct reset_control *por_reset;
struct reset_control *phy_reset;
+ struct reset_control *ext_reset;
struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
};
@@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
if (IS_ERR(res->por_reset))
return PTR_ERR(res->por_reset);
+ res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
+ if (IS_ERR(res->ext_reset))
+ return PTR_ERR(res->ext_reset);
+
res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
return PTR_ERR_OR_ZERO(res->phy_reset);
}
@@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
+ reset_control_assert(res->ext_reset);
reset_control_assert(res->phy_reset);
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
@@ -347,6 +353,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_deassert_ahb;
}
+ ret = reset_control_deassert(res->ext_reset);
+ if (ret) {
+ dev_err(dev, "cannot assert ext reset\n");
+ goto err_deassert_ahb;
+ }
+
/* enable PCIe clocks and resets */
val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
val &= ~BIT(0);
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v3 04/11] PCI: qcom: add missing reset for ipq806x
2020-04-30 22:06 ` [PATCH v3 04/11] PCI: qcom: add missing reset for ipq806x Ansuel Smith
@ 2020-05-07 18:00 ` Rob Herring
2020-05-08 7:20 ` Philipp Zabel
1 sibling, 0 replies; 8+ messages in thread
From: Rob Herring @ 2020-05-07 18:00 UTC (permalink / raw)
To: Ansuel Smith
Cc: Bjorn Andersson, Ansuel Smith, Sham Muthayyan, stable, Andy Gross,
Bjorn Helgaas, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
On Fri, 1 May 2020 00:06:11 +0200, Ansuel Smith wrote:
> Add missing ext reset used by ipq8064 SoC in PCIe qcom driver.
>
> Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver
> Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Cc: stable@vger.kernel.org # v4.5+
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 04/11] PCI: qcom: add missing reset for ipq806x
2020-04-30 22:06 ` [PATCH v3 04/11] PCI: qcom: add missing reset for ipq806x Ansuel Smith
2020-05-07 18:00 ` Rob Herring
@ 2020-05-08 7:20 ` Philipp Zabel
1 sibling, 0 replies; 8+ messages in thread
From: Philipp Zabel @ 2020-05-08 7:20 UTC (permalink / raw)
To: Ansuel Smith
Cc: Bjorn Andersson, Sham Muthayyan, stable, Andy Gross,
Bjorn Helgaas, Rob Herring, Mark Rutland, Stanimir Varbanov,
Lorenzo Pieralisi, Andrew Murray, linux-arm-msm, linux-pci,
devicetree, linux-kernel
Hi Ansuel,
On Fri, May 01, 2020 at 12:06:11AM +0200, Ansuel Smith wrote:
> Add missing ext reset used by ipq8064 SoC in PCIe qcom driver.
>
> Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver
> Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Cc: stable@vger.kernel.org # v4.5+
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 7a8901efc031..921030a64bab 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
[...]
> @@ -347,6 +353,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
> goto err_deassert_ahb;
> }
>
> + ret = reset_control_deassert(res->ext_reset);
> + if (ret) {
> + dev_err(dev, "cannot assert ext reset\n");
^
This probably should say "cannot deassert ext reset". Apart from this,
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
regards
Philipp
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 07/11] PCI: qcom: add support for defining some PARF params
[not found] <20200430220619.3169-1-ansuelsmth@gmail.com>
2020-04-30 22:06 ` [PATCH v3 01/11] PCI: qcom: add missing ipq806x clocks in PCIe driver Ansuel Smith
2020-04-30 22:06 ` [PATCH v3 04/11] PCI: qcom: add missing reset for ipq806x Ansuel Smith
@ 2020-04-30 22:06 ` Ansuel Smith
2 siblings, 0 replies; 8+ messages in thread
From: Ansuel Smith @ 2020-04-30 22:06 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ansuel Smith, stable, Andy Gross, Bjorn Helgaas, Rob Herring,
Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray,
Philipp Zabel, linux-arm-msm, linux-pci, devicetree, linux-kernel
Add support for Tx De-Emphasis, Tx Swing and Rx equalization definition
needed on some ipq8064 based device (Netgear R7800 for example). This
cause a total lock of the system on kernel load.
Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v4.5+
---
drivers/pci/controller/dwc/pcie-qcom.c | 47 ++++++++++++++++++++++++--
1 file changed, 45 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index a4fd5baada34..da8058fd1925 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -46,6 +46,9 @@
#define PCIE20_PARF_PHY_CTRL 0x40
#define PCIE20_PARF_PHY_REFCLK 0x4C
+#define PHY_REFCLK_SSP_EN BIT(16)
+#define PHY_REFCLK_USE_PAD BIT(12)
+
#define PCIE20_PARF_DBI_BASE_ADDR 0x168
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
@@ -77,6 +80,18 @@
#define DBI_RO_WR_EN 1
#define PERST_DELAY_US 1000
+/* PARF registers */
+#define PCIE20_PARF_PCS_DEEMPH 0x34
+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
+
+#define PCIE20_PARF_PCS_SWING 0x38
+#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
+#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
+
+#define PCIE20_PARF_CONFIG_BITS 0x50
+#define PHY_RX0_EQ(x) ((x) << 24)
#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
#define SLV_ADDR_SPACE_SZ 0x10000000
@@ -97,6 +112,12 @@ struct qcom_pcie_resources_2_1_0 {
struct reset_control *phy_reset;
struct reset_control *ext_reset;
struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
+ u32 tx_deemph_gen1;
+ u32 tx_deemph_gen2_3p5db;
+ u32 tx_deemph_gen2_6db;
+ u32 tx_swing_full;
+ u32 tx_swing_low;
+ u32 rx0_eq;
};
struct qcom_pcie_resources_1_0_0 {
@@ -234,8 +255,21 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
+ struct device_node *node = dev->of_node;
int ret;
+ of_property_read_u32(node, "qcom,tx-deemph-gen1",
+ &res->tx_deemph_gen1);
+ of_property_read_u32(node, "qcom,tx-deemph-gen2-3p5db",
+ &res->tx_deemph_gen2_3p5db);
+ of_property_read_u32(node, "qcom,tx-deemph-gen2-6db",
+ &res->tx_deemph_gen2_6db);
+ of_property_read_u32(node, "qcom,tx-swing-full",
+ &res->tx_swing_full);
+ of_property_read_u32(node, "qcom,tx-swing-low",
+ &res->tx_swing_low);
+ of_property_read_u32(node, "qcom,rx0-eq", &res->rx0_eq);
+
res->supplies[0].supply = "vdda";
res->supplies[1].supply = "vdda_phy";
res->supplies[2].supply = "vdda_refclk";
@@ -368,9 +402,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
/* enable PCIe clocks and resets */
qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
+ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(res->tx_deemph_gen1) |
+ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(res->tx_deemph_gen2_3p5db) |
+ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(res->tx_deemph_gen2_6db),
+ pcie->parf + PCIE20_PARF_PCS_DEEMPH);
+ writel(PCS_SWING_TX_SWING_FULL(res->tx_swing_full) |
+ PCS_SWING_TX_SWING_LOW(res->tx_swing_low),
+ pcie->parf + PCIE20_PARF_PCS_SWING);
+ writel(PHY_RX0_EQ(res->rx0_eq), pcie->parf + PCIE20_PARF_CONFIG_BITS);
+
/* enable external reference clock */
- qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_REFCLK, 0,
- BIT(16));
+ qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_REFCLK,
+ PHY_REFCLK_USE_PAD, PHY_REFCLK_SSP_EN;
ret = reset_control_deassert(res->phy_reset);
if (ret) {
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread