From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1E90C433E0 for ; Tue, 23 Jun 2020 20:25:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7EE8E20702 for ; Tue, 23 Jun 2020 20:25:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592943927; bh=85x603QGwRYhwyd9lx9+P6kxEIy58DHQWEFU5nMXChU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=lIE9HV1Tr1+FKM15qh9xLq8zKAc6FHzFJD3lhGl8b6Rojl2MVzlIzxBBnqM6LlYvX hCzFOFjq6vbCXELpoQrI9Dq/KU1CLdA4LVqjDIRVGPoCTg9CHBLgzTxmf0mGwmesZW +0rUIE7CGzjHLJFjy1/crmId9ouHscEe+AbcnBAE= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390550AbgFWUZ0 (ORCPT ); Tue, 23 Jun 2020 16:25:26 -0400 Received: from mail.kernel.org ([198.145.29.99]:44354 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389986AbgFWUZZ (ORCPT ); Tue, 23 Jun 2020 16:25:25 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 45B0A206EB; Tue, 23 Jun 2020 20:25:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592943924; bh=85x603QGwRYhwyd9lx9+P6kxEIy58DHQWEFU5nMXChU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=omPABZQ9M6eJQsQGXmwR1K7i7YP0ef8UYTDUWOC1aOyl5YnBL1SCub+8aUl3z+jCY WFhm0xBekhJpHDELZCJqmLs8/KfbLC/Viu711Ls6yvMK3AbUqNQkWxy/5chXufJuiz 5SQkxdl7OVcqyA7slrbYNiCEkZK+rmarvg2wH8JU= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Neil Armstrong , Martin Blumenstingl , Jerome Brunet , Sasha Levin Subject: [PATCH 5.4 105/314] clk: meson: meson8b: Fix the first parent of vid_pll_in_sel Date: Tue, 23 Jun 2020 21:55:00 +0200 Message-Id: <20200623195343.865467987@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200623195338.770401005@linuxfoundation.org> References: <20200623195338.770401005@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Martin Blumenstingl [ Upstream commit da1978ac3d6cf278dedf5edbf350445a0fff2f08 ] Use hdmi_pll_lvds_out as parent of the vid_pll_in_sel clock. It's not easy to see that the vendor kernel does the same, but it actually does. meson_clk_pll_ops in mainline still cannot fully recalculate all rates from the HDMI PLL registers because some register bits (at the time of writing it's unknown which bits are used for this) double the HDMI PLL output rate (compared to simply considering M, N and FRAC) for some (but not all) PLL settings. Update the vid_pll_in_sel parent so our clock calculation works for simple clock settings like the CVBS output (where no rate doubling is going on). The PLL ops need to be fixed later on for more complex clock settings (all HDMI rates). Fixes: 6cb57c678bb70 ("clk: meson: meson8b: add the read-only video clock trees") Suggested-by: Neil Armstrong Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20200417184127.1319871-2-martin.blumenstingl@googlemail.com Signed-off-by: Sasha Levin --- drivers/clk/meson/meson8b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 8856ce476ccfa..ab0b56daec548 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -1071,7 +1071,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = { * Meson8m2: vid2_pll */ .parent_hws = (const struct clk_hw *[]) { - &meson8b_hdmi_pll_dco.hw + &meson8b_hdmi_pll_lvds_out.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- 2.25.1