From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6F2FC433E0 for ; Tue, 14 Jul 2020 19:07:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B94EE21D79 for ; Tue, 14 Jul 2020 19:07:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1594753659; bh=PtD6kzJHepOAdrv/PmWvzqv98Ct/bG4qvEQTAwnaIM0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=eit/5KrxGs71dyt8M7bkM4q8ACUmVCipVgMIkmmK8Fwjh/r69X/ceqBmsOjhBnVU8 Ljk6OEHzG0UpgQHKWE6Sg9krkcb4Xc6RV12shU5IR7+qNiGwR39tPD+hp7v8Wymndd 6gF8mlP7KdwImvi9L7pyPe2HgBCzOuSOFXfZs+R4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729124AbgGNSvx (ORCPT ); Tue, 14 Jul 2020 14:51:53 -0400 Received: from mail.kernel.org ([198.145.29.99]:48430 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730438AbgGNSvv (ORCPT ); Tue, 14 Jul 2020 14:51:51 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5320C22B47; Tue, 14 Jul 2020 18:51:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1594752710; bh=PtD6kzJHepOAdrv/PmWvzqv98Ct/bG4qvEQTAwnaIM0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=krxwT34G2Mrq9BTWY6rHhSb4L5P4GKUASredrODBjjBYDar/Dwz4sosyPFpCfvqo4 fE3HTBBBmN+S/CUcLqKWA/ExD967tonS+wpDiSCTwCGWNpH4EuSgzbE6/kLop1uTgf q/nb6aGX3T0aa9BFWtgCcWk1RBa9yoiw0VL+3KlE= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Adrian Hunter , Jiri Olsa , Luwei Kang , Arnaldo Carvalho de Melo , Sasha Levin Subject: [PATCH 5.4 050/109] perf intel-pt: Fix PEBS sample for XMM registers Date: Tue, 14 Jul 2020 20:43:53 +0200 Message-Id: <20200714184107.917340584@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200714184105.507384017@linuxfoundation.org> References: <20200714184105.507384017@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Adrian Hunter [ Upstream commit 4c95ad261cfac120dd66238fcae222766754c219 ] The condition to add XMM registers was missing, the regs array needed to be in the outer scope, and the size of the regs array was too small. Fixes: 143d34a6b387b ("perf intel-pt: Add XMM registers to synthesized PEBS sample") Signed-off-by: Adrian Hunter Cc: Jiri Olsa Cc: Luwei Kang Link: http://lore.kernel.org/lkml/20200630133935.11150-4-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/util/intel-pt.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c index a1c9eb6d4f40d..c5cce3a60476b 100644 --- a/tools/perf/util/intel-pt.c +++ b/tools/perf/util/intel-pt.c @@ -1707,6 +1707,7 @@ static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq) u64 sample_type = evsel->core.attr.sample_type; u64 id = evsel->core.id[0]; u8 cpumode; + u64 regs[8 * sizeof(sample.intr_regs.mask)]; if (intel_pt_skip_event(pt)) return 0; @@ -1756,8 +1757,8 @@ static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq) } if (sample_type & PERF_SAMPLE_REGS_INTR && - items->mask[INTEL_PT_GP_REGS_POS]) { - u64 regs[sizeof(sample.intr_regs.mask)]; + (items->mask[INTEL_PT_GP_REGS_POS] || + items->mask[INTEL_PT_XMM_POS])) { u64 regs_mask = evsel->core.attr.sample_regs_intr; u64 *pos; -- 2.25.1