From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A054C433F4 for ; Tue, 14 Jul 2020 19:04:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 490CD22B4E for ; Tue, 14 Jul 2020 19:04:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1594753451; bh=uH0PDz0zA3uX9zg+dvKMu8xWqiGXeFBXQbz58FsVmRs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=2laJNOuAaaObQ+4Zg6yfk3byFpJZW3BiKWLfHBSMGx10kxwRv0AATAFouGIEt7H7t D6HOiAhMuoHHcBtN+GqlCan+oo+6TTV9KJ0ysn6xrgknKdC44+yT+4nTzOwte0qdxt IqBgZairapsw/ZthvfKpNzzZAoLXYRbK2WB7QKKg= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729826AbgGNS4V (ORCPT ); Tue, 14 Jul 2020 14:56:21 -0400 Received: from mail.kernel.org ([198.145.29.99]:54248 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730970AbgGNS4U (ORCPT ); Tue, 14 Jul 2020 14:56:20 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id ACD4A222B9; Tue, 14 Jul 2020 18:56:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1594752980; bh=uH0PDz0zA3uX9zg+dvKMu8xWqiGXeFBXQbz58FsVmRs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TqVC7l7MRPMI7gN4HUTb1KwoFUJMTmYZBIy0N72NwjZsvROTGk4v27AVkBqokM5Uq fcqOW3UqnBsno8u0O50N95BLBRCbE3T62hStwC0XlDtRc+F+QgdKH4FxdaJ1xrncyq 9LTq5cbusgchT0OzeDLj8xw5b9mYSjLv5NR1l934= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Adrian Hunter , Jiri Olsa , Luwei Kang , Arnaldo Carvalho de Melo , Sasha Levin Subject: [PATCH 5.7 074/166] perf intel-pt: Fix PEBS sample for XMM registers Date: Tue, 14 Jul 2020 20:43:59 +0200 Message-Id: <20200714184119.398711366@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200714184115.844176932@linuxfoundation.org> References: <20200714184115.844176932@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Adrian Hunter [ Upstream commit 4c95ad261cfac120dd66238fcae222766754c219 ] The condition to add XMM registers was missing, the regs array needed to be in the outer scope, and the size of the regs array was too small. Fixes: 143d34a6b387b ("perf intel-pt: Add XMM registers to synthesized PEBS sample") Signed-off-by: Adrian Hunter Cc: Jiri Olsa Cc: Luwei Kang Link: http://lore.kernel.org/lkml/20200630133935.11150-4-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/util/intel-pt.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c index 23c8289c2472d..545d1cdc0ec87 100644 --- a/tools/perf/util/intel-pt.c +++ b/tools/perf/util/intel-pt.c @@ -1731,6 +1731,7 @@ static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq) u64 sample_type = evsel->core.attr.sample_type; u64 id = evsel->core.id[0]; u8 cpumode; + u64 regs[8 * sizeof(sample.intr_regs.mask)]; if (intel_pt_skip_event(pt)) return 0; @@ -1780,8 +1781,8 @@ static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq) } if (sample_type & PERF_SAMPLE_REGS_INTR && - items->mask[INTEL_PT_GP_REGS_POS]) { - u64 regs[sizeof(sample.intr_regs.mask)]; + (items->mask[INTEL_PT_GP_REGS_POS] || + items->mask[INTEL_PT_XMM_POS])) { u64 regs_mask = evsel->core.attr.sample_regs_intr; u64 *pos; -- 2.25.1