From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85C23C433FE for ; Mon, 20 Jul 2020 16:36:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 56B7D22CBE for ; Mon, 20 Jul 2020 16:36:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1595262981; bh=a1wX56O3UUk6wUvl7vJKE53fpz3FbSKZ3H8oA4dNQJ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=b4U0zcJWxcvaMlfubtPhTgknoWKwlOclXfw4f0QhfyonqlW2rouIDHx7osmkgJVwu r2weFJCp7mqpGct2L/n+fqCrFaaaK0RFcj/LMGd6tafVeKa8JhSLP+eucPB9Nv+OFh /mzNDx7Hvqo69RyXAl7fj2YX6R+taXNzHtXX0WuM= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730834AbgGTPxG (ORCPT ); Mon, 20 Jul 2020 11:53:06 -0400 Received: from mail.kernel.org ([198.145.29.99]:51376 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730407AbgGTPxD (ORCPT ); Mon, 20 Jul 2020 11:53:03 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 534392065E; Mon, 20 Jul 2020 15:53:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1595260382; bh=a1wX56O3UUk6wUvl7vJKE53fpz3FbSKZ3H8oA4dNQJ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ThFE8RRhKDAfbVxwt0HguHxU3srI1HxO/oq6kxSs33jb8HvM2xnUYhfffabWl/hmU ZaDGWjZ8d7qW0Id74IvQq9PMXqT6zLFo1umCO9sRZbm3b6OIYhLzSQhxmQJMNYpG7P ULoGLDkFBGfokyhnhFFFywuJR3+LGnBa0rInGppI= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Krzysztof Kozlowski , Dinh Nguyen , Sasha Levin Subject: [PATCH 4.19 065/133] ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema Date: Mon, 20 Jul 2020 17:36:52 +0200 Message-Id: <20200720152806.877714633@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200720152803.732195882@linuxfoundation.org> References: <20200720152803.732195882@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Krzysztof Kozlowski [ Upstream commit d7adfe5ffed9faa05f8926223086b101e14f700d ] Fix dtschema validator warnings like: l2-cache@fffff000: $nodename:0: 'l2-cache@fffff000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Fixes: 475dc86d08de ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC") Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen Signed-off-by: Sasha Levin --- arch/arm/boot/dts/socfpga.dtsi | 2 +- arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index b38f8c2405580..602511ccad6f6 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -710,7 +710,7 @@ ocram-ecc@ffd08144 { }; }; - L2: l2-cache@fffef000 { + L2: cache-controller@fffef000 { compatible = "arm,pl310-cache"; reg = <0xfffef000 0x1000>; interrupts = <0 38 0x04>; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index b4dd3846e8cc9..ba5657574d9bb 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -618,7 +618,7 @@ sdr: sdr@ffcfb100 { reg = <0xffcfb100 0x80>; }; - L2: l2-cache@fffff000 { + L2: cache-controller@fffff000 { compatible = "arm,pl310-cache"; reg = <0xfffff000 0x1000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; -- 2.25.1