From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84C21C433E0 for ; Mon, 10 Aug 2020 19:28:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 65EE122CA1 for ; Mon, 10 Aug 2020 19:28:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597087719; bh=USN0Q1T9sE6yZpQz7cHcvRFMEmyBPpCpKUSkznsy/i4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=z6Ma81orakmJ1nWff3yXXo+58x5nKLq84RSqETQLkGJOvKTnuFCCQUBe2RPfP9a0H yAbIEP4vybepyJpv9LPQgHVnRnb2WR1TDoWVqQT11ko9Eu8h6ucx0GsmQebNo2Gfzv xlFX+qNOKV34jQNmb3rRkezRRG/3LrHBSpCLtzk8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729152AbgHJTLF (ORCPT ); Mon, 10 Aug 2020 15:11:05 -0400 Received: from mail.kernel.org ([198.145.29.99]:39030 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729130AbgHJTLD (ORCPT ); Mon, 10 Aug 2020 15:11:03 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id D4903221E2; Mon, 10 Aug 2020 19:11:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597086663; bh=USN0Q1T9sE6yZpQz7cHcvRFMEmyBPpCpKUSkznsy/i4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GhvfWsGotGIOrLRtQyYSHxjIMt/F6e2z7mKzmjTuyPSSe7pcW8MfMj7B7bnQNuPAV cC/OLbmkgZl46sgcbBF1R7jtwkmyJOlGAxu1xPuEuPW4ATURLEv316NCwOGa2BV5GS j0ZZ/99VHjncm0no6Azsbz/xzubDl9QO7cvlble0= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Akhil P Oommen , Matthias Kaehlcke , Jordan Crouse , Rob Clark , Sasha Levin , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH AUTOSEL 5.7 25/60] drm: msm: a6xx: fix gpu failure after system resume Date: Mon, 10 Aug 2020 15:09:53 -0400 Message-Id: <20200810191028.3793884-25-sashal@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200810191028.3793884-1-sashal@kernel.org> References: <20200810191028.3793884-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Akhil P Oommen [ Upstream commit 57c0bd517c06b088106b0236ed604056c8e06da5 ] On targets where GMU is available, GMU takes over the ownership of GX GDSC during its initialization. So, move the refcount-get on GX PD before we initialize the GMU. This ensures that nobody can collapse the GX GDSC once GMU owns the GX GDSC. This patch fixes some GMU OOB errors seen during GPU wake up during a system resume. Reported-by: Matthias Kaehlcke Signed-off-by: Akhil P Oommen Tested-by: Matthias Kaehlcke Reviewed-by: Jordan Crouse Signed-off-by: Rob Clark Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 34607a98cc7c8..9a7a18951dc2b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -732,10 +732,19 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) /* Turn on the resources */ pm_runtime_get_sync(gmu->dev); + /* + * "enable" the GX power domain which won't actually do anything but it + * will make sure that the refcounting is correct in case we need to + * bring down the GX after a GMU failure + */ + if (!IS_ERR_OR_NULL(gmu->gxpd)) + pm_runtime_get_sync(gmu->gxpd); + /* Use a known rate to bring up the GMU */ clk_set_rate(gmu->core_clk, 200000000); ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); if (ret) { + pm_runtime_put(gmu->gxpd); pm_runtime_put(gmu->dev); return ret; } @@ -771,19 +780,12 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) /* Set the GPU to the current freq */ __a6xx_gmu_set_freq(gmu, gmu->current_perf_index); - /* - * "enable" the GX power domain which won't actually do anything but it - * will make sure that the refcounting is correct in case we need to - * bring down the GX after a GMU failure - */ - if (!IS_ERR_OR_NULL(gmu->gxpd)) - pm_runtime_get(gmu->gxpd); - out: /* On failure, shut down the GMU to leave it in a good state */ if (ret) { disable_irq(gmu->gmu_irq); a6xx_rpmh_stop(gmu); + pm_runtime_put(gmu->gxpd); pm_runtime_put(gmu->dev); } -- 2.25.1