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From: Vinod Koul <vkoul@kernel.org>
To: Gustavo Pimentel <Gustavo.Pimentel@synopsys.com>
Cc: dmaengine@vger.kernel.org, Joao Pinto <Joao.Pinto@synopsys.com>,
	stable@vger.kernel.org
Subject: Re: [PATCH] dmaengine: dw-edma: Fix linked list physical address calculation on non-64 bits architectures
Date: Tue, 25 Aug 2020 16:39:37 +0530	[thread overview]
Message-ID: <20200825110937.GI2639@vkoul-mobl> (raw)
In-Reply-To: <9d92b3c0f9304e3f2892833a70c726b911b29fd8.1597327637.git.gustavo.pimentel@synopsys.com>

On 13-08-20, 16:13, Gustavo Pimentel wrote:
> Fix linked list physical address calculation on non-64 bits architectures.
> 
> The paddr variable is phys_addr_t type, which can assume a different
> type (u64 or u32) depending on the conditional compilation flag
> CONFIG_PHYS_ADDR_T_64BIT.
> 
> Since this variable is used in with upper_32 bits() macro to get the
> value from 32 to 63 bits, on a non-64 bits architecture this variable
> will assume a u32 type, it can cause a compilation warning.
> 
> This issue was reported by a Coverity analysis.
> 
> Fixes: 7e4b8a4fbe2c ("dmaengine: Add Synopsys eDMA IP version 0 support")
> 
> Cc: Joao Pinto <jpinto@synopsys.com>
> Cc: stable@vger.kernel.org
> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> ---
>  drivers/dma/dw-edma/dw-edma-v0-core.c | 23 +++++++++++++++++------
>  1 file changed, 17 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
> index 692de47..cfabbf5 100644
> --- a/drivers/dma/dw-edma/dw-edma-v0-core.c
> +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
> @@ -229,8 +229,13 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
>  	/* Channel control */
>  	SET_LL(&llp->control, control);
>  	/* Linked list  - low, high */
> -	SET_LL(&llp->llp_low, lower_32_bits(chunk->ll_region.paddr));
> -	SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr));
> +	#ifdef CONFIG_PHYS_ADDR_T_64BIT
> +		SET_LL(&llp->llp_low, lower_32_bits(chunk->ll_region.paddr));
> +		SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr));
> +	#else /* CONFIG_PHYS_ADDR_T_64BIT */
> +		SET_LL(&llp->llp_low, chunk->ll_region.paddr);
> +		SET_LL(&llp->llp_high, 0x0);

Shouldn't upper_32_bits(chunk->ll_region.paddr) return zero for non
64bit archs?

> +	#endif /* CONFIG_PHYS_ADDR_T_64BIT */
>  }
>  
>  void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
> @@ -257,10 +262,16 @@ void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
>  		SET_CH(dw, chan->dir, chan->id, ch_control1,
>  		       (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE));
>  		/* Linked list - low, high */
> -		SET_CH(dw, chan->dir, chan->id, llp_low,
> -		       lower_32_bits(chunk->ll_region.paddr));
> -		SET_CH(dw, chan->dir, chan->id, llp_high,
> -		       upper_32_bits(chunk->ll_region.paddr));
> +		#ifdef CONFIG_PHYS_ADDR_T_64BIT
> +			SET_CH(dw, chan->dir, chan->id, llp_low,
> +			       lower_32_bits(chunk->ll_region.paddr));
> +			SET_CH(dw, chan->dir, chan->id, llp_high,
> +			       upper_32_bits(chunk->ll_region.paddr));
> +		#else /* CONFIG_PHYS_ADDR_T_64BIT */
> +			SET_CH(dw, chan->dir, chan->id, llp_low,
> +			       chunk->ll_region.paddr);
> +			SET_CH(dw, chan->dir, chan->id, llp_high, 0x0);
> +		#endif /* CONFIG_PHYS_ADDR_T_64BIT*/
>  	}
>  	/* Doorbell */
>  	SET_RW(dw, chan->dir, doorbell,
> -- 
> 2.7.4

-- 
~Vinod

  parent reply	other threads:[~2020-08-25 11:09 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-13 14:13 [PATCH] dmaengine: dw-edma: Fix linked list physical address calculation on non-64 bits architectures Gustavo Pimentel
2020-08-13 17:07 ` kernel test robot
2020-08-25 11:09 ` Vinod Koul [this message]
2020-08-26 12:31   ` Gustavo Pimentel
2020-08-27  5:10     ` Vinod Koul

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