From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E6E3C55178 for ; Tue, 3 Nov 2020 20:51:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2323E22447 for ; Tue, 3 Nov 2020 20:51:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1604436663; bh=aQ5aSdQp7TX/YQjR1D8fatRK/f8bsdBrids+DXenPhY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=iNQobY9v6QoOL86Ztovqb7GDBR/9oGtFA7dHqGVshzYxnQ0cbQlylrKAL5ffiCG+F 9SLy6sq2tYIOwdnJvWTi0QyNM7D3kfW0eY/IUdS2Fm5hOg8X7NZZLz3q44XJlapqpP 1MU5ilex84fxAw8oWUTUluHfmSWnykBzs+LLuIoI= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731861AbgKCUvB (ORCPT ); Tue, 3 Nov 2020 15:51:01 -0500 Received: from mail.kernel.org ([198.145.29.99]:45626 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731892AbgKCUvA (ORCPT ); Tue, 3 Nov 2020 15:51:00 -0500 Received: from localhost (83-86-74-64.cable.dynamic.v4.ziggo.nl [83.86.74.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A2DAF20719; Tue, 3 Nov 2020 20:50:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1604436660; bh=aQ5aSdQp7TX/YQjR1D8fatRK/f8bsdBrids+DXenPhY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m4n9R1KJzqyPBQAa4ghFdPGysl4D/snlQsF8rDi1uHOdP0vHLR6xYKstsSjXXtimD NZ00a0Ff0luY+2TkM/DPsYt05Pf8WioDuy9RvBNIty8FDa3EOYp+9PPqybSjUWX3jx e50dqLwNcDpHQt/c4xCDj8Jh5MaVpv1KugngsYCs= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Kim Phillips , Ian Rogers , Alexander Shishkin , Andi Kleen , Borislav Petkov , Jin Yao , Jiri Olsa , John Garry , Jon Grimm , Kan Liang , Mark Rutland , Martin Jambor , =?UTF-8?q?Martin=20Li=C5=A1ka?= , Michael Petlan , Namhyung Kim , Peter Zijlstra , Stephane Eranian , Vijay Thakkar , William Cohen , Yunfeng Ye , Arnaldo Carvalho de Melo Subject: [PATCH 5.9 309/391] perf vendor events amd: Add L2 Prefetch events for zen1 Date: Tue, 3 Nov 2020 21:36:00 +0100 Message-Id: <20201103203407.957958940@linuxfoundation.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201103203348.153465465@linuxfoundation.org> References: <20201103203348.153465465@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Kim Phillips commit 60d804521ec4cd01217a96f33cd1bb29e295333d upstream. Later revisions of PPRs that post-date the original Family 17h events submission patch add these events. Specifically, they were not in this 2017 revision of the F17h PPR: Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors Rev 1.14 - April 15, 2017 But e.g., are included in this 2019 version of the PPR: Processor Programming Reference (PPR) for AMD Family 17h Model 18h, Revision B1 Processors Rev. 3.14 - Sep 26, 2019 Fixes: 98c07a8f74f8 ("perf vendor events amd: perf PMU events for AMD Family 17h") Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Kim Phillips Reviewed-by: Ian Rogers Cc: Alexander Shishkin Cc: Andi Kleen Cc: Borislav Petkov Cc: Jin Yao Cc: Jiri Olsa Cc: John Garry Cc: Jon Grimm Cc: Kan Liang Cc: Mark Rutland Cc: Martin Jambor Cc: Martin Liška Cc: Michael Petlan Cc: Namhyung Kim Cc: Peter Zijlstra Cc: stable@vger.kernel.org Cc: Stephane Eranian Cc: Vijay Thakkar Cc: William Cohen Cc: Yunfeng Ye Link: http://lore.kernel.org/lkml/20200901220944.277505-1-kim.phillips@amd.com Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Greg Kroah-Hartman --- tools/perf/pmu-events/arch/x86/amdzen1/cache.json | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) --- a/tools/perf/pmu-events/arch/x86/amdzen1/cache.json +++ b/tools/perf/pmu-events/arch/x86/amdzen1/cache.json @@ -250,6 +250,24 @@ "UMask": "0x1" }, { + "EventName": "l2_pf_hit_l2", + "EventCode": "0x70", + "BriefDescription": "L2 prefetch hit in L2.", + "UMask": "0xff" + }, + { + "EventName": "l2_pf_miss_l2_hit_l3", + "EventCode": "0x71", + "BriefDescription": "L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.", + "UMask": "0xff" + }, + { + "EventName": "l2_pf_miss_l2_l3", + "EventCode": "0x72", + "BriefDescription": "L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches.", + "UMask": "0xff" + }, + { "EventName": "l3_request_g1.caching_l3_cache_accesses", "EventCode": "0x01", "BriefDescription": "Caching: L3 cache accesses",