From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 571ADC433EF for ; Thu, 25 Nov 2021 00:31:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245407AbhKYAeL (ORCPT ); Wed, 24 Nov 2021 19:34:11 -0500 Received: from mail.kernel.org ([198.145.29.99]:46912 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345006AbhKYAbm (ORCPT ); Wed, 24 Nov 2021 19:31:42 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 4A21A610F9; Thu, 25 Nov 2021 00:26:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637800003; bh=vdBbh9Twp1v/l+LA/5VYiipV1bwbRcD60GbxylV6JAE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NIKkdI7pKjoetZxwyurVN6y1HnPql1Q5u0JD2h1m1Mw5oGixj8Ahd1iJLLPKPAmJe YZmXnWm0PfIcCvz7oKckdsx5I3YegR3l+OZsnInY4HyTCBrLLwPuuoNoSNHX68BgkL fYwTmUfaJycF8B1wyG8CAHAmyV26aPQvSJM23Oyg0e61ZtrCe6D1T1esWeE+RWtyEs ujPFlp2ieXRW0di7Dh1x9HGdIZEIKLiW5WHMlqvgAKcBWicmHfAcA46L7n32klQ7/l cz77u8XBkgENxpcSfCPJtpBdygpZOJ1EioWGcKGPtl8k70i1h6gaEYmvdUcXqtY5Mq HtTsnfYeD9PSw== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Greg Kroah-Hartman , Sasha Levin Cc: pali@kernel.org, stable@vger.kernel.org, =?UTF-8?q?Marek=20Beh=C3=BAn?= , Lorenzo Pieralisi Subject: [PATCH 5.4 13/22] PCI: aardvark: Fix PCIe Max Payload Size setting Date: Thu, 25 Nov 2021 01:26:07 +0100 Message-Id: <20211125002616.31363-14-kabel@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211125002616.31363-1-kabel@kernel.org> References: <20211125002616.31363-1-kabel@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Pali Rohár commit a4e17d65dafdd3513042d8f00404c9b6068a825c upstream. Change PCIe Max Payload Size setting in PCIe Device Control register to 512 bytes to align with PCIe Link Initialization sequence as defined in Marvell Armada 3700 Functional Specification. According to the specification, maximal Max Payload Size supported by this device is 512 bytes. Without this kernel prints suspicious line: pci 0000:01:00.0: Upstream bridge's Max Payload Size set to 256 (was 16384, max 512) With this change it changes to: pci 0000:01:00.0: Upstream bridge's Max Payload Size set to 256 (was 512, max 512) Link: https://lore.kernel.org/r/20211005180952.6812-3-kabel@kernel.org Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Signed-off-by: Lorenzo Pieralisi Reviewed-by: Marek Behún Cc: stable@vger.kernel.org Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 570f8c62b459..ef4555a28b95 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -565,8 +565,9 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); reg &= ~PCI_EXP_DEVCTL_RELAX_EN; reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; + reg &= ~PCI_EXP_DEVCTL_PAYLOAD; reg &= ~PCI_EXP_DEVCTL_READRQ; - reg |= PCI_EXP_DEVCTL_PAYLOAD; /* Set max payload size */ + reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; reg |= PCI_EXP_DEVCTL_READRQ_512B; advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); -- 2.32.0