From: Aurelien Jarno <aurelien@aurel32.net>
To: linux-kernel@vger.kernel.org
Cc: Aurelien Jarno <aurelien@aurel32.net>,
stable@vger.kernel.org, Kito Cheng <kito.cheng@gmail.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE)
Subject: [PATCH] riscv: fix build with binutils 2.38
Date: Wed, 26 Jan 2022 18:14:42 +0100 [thread overview]
Message-ID: <20220126171442.1338740-1-aurelien@aurel32.net> (raw)
From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr read/write (csrr*/csrw*) instructions and fence.i
instruction has separated from the `I` extension, become two standalone
extensions: Zicsr and Zifencei. As the kernel uses those instruction,
this causes the following build failure:
CC arch/riscv/kernel/vdso/vgettimeofday.o
<<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages:
<<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
<<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
<<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
<<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
The fix is to specify those extensions explicitely in -march. However as
older binutils version do not support this, we first need to detect
that.
Cc: stable@vger.kernel.org # 4.15+
Cc: Kito Cheng <kito.cheng@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
arch/riscv/Makefile | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 8a107ed18b0d..7d81102cffd4 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
+
+# Newer binutils versions default to ISA spec version 20191213 which moves some
+# instructions from the I extension to the Zicsr and Zifencei extensions.
+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
+riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
+
KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
KBUILD_AFLAGS += -march=$(riscv-march-y)
--
2.34.1
next reply other threads:[~2022-01-26 17:47 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-26 17:14 Aurelien Jarno [this message]
2022-01-28 10:05 ` [PATCH] riscv: fix build with binutils 2.38 Alexandre Ghiti
2022-02-10 17:40 ` Palmer Dabbelt
2022-02-10 17:56 ` Greg KH
2022-03-31 10:32 ` Marc Kleine-Budde
2022-03-31 10:39 ` Marc Kleine-Budde
2022-03-31 10:51 ` Marc Kleine-Budde
2022-03-31 17:05 ` Aurelien Jarno
2022-03-31 18:16 ` Linus Torvalds
2022-03-31 19:42 ` Palmer Dabbelt
2022-04-01 6:53 ` Marc Kleine-Budde
2022-04-01 17:14 ` Linus Torvalds
2022-04-01 17:55 ` Palmer Dabbelt
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