* FAILED: patch "[PATCH] x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN" failed to apply to 5.10-stable tree
@ 2022-01-30 12:34 gregkh
2022-01-31 17:16 ` Luck, Tony
0 siblings, 1 reply; 6+ messages in thread
From: gregkh @ 2022-01-30 12:34 UTC (permalink / raw)
To: tony.luck, ailin.xu, bp, stable; +Cc: stable
The patch below does not apply to the 5.10-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to <stable@vger.kernel.org>.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From e464121f2d40eabc7d11823fb26db807ce945df4 Mon Sep 17 00:00:00 2001
From: Tony Luck <tony.luck@intel.com>
Date: Fri, 21 Jan 2022 09:47:38 -0800
Subject: [PATCH] x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN
Missed adding the Icelake-D CPU to the list. It uses the same MSRs
to control and read the inventory number as all the other models.
Fixes: dc6b025de95b ("x86/mce: Add Xeon Icelake to list of CPUs that support PPIN")
Reported-by: Ailin Xu <ailin.xu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220121174743.1875294-2-tony.luck@intel.com
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index bb9a46a804bf..baafbb37be67 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
case INTEL_FAM6_BROADWELL_X:
case INTEL_FAM6_SKYLAKE_X:
case INTEL_FAM6_ICELAKE_X:
+ case INTEL_FAM6_ICELAKE_D:
case INTEL_FAM6_SAPPHIRERAPIDS_X:
case INTEL_FAM6_XEON_PHI_KNL:
case INTEL_FAM6_XEON_PHI_KNM:
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: FAILED: patch "[PATCH] x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN" failed to apply to 5.10-stable tree
2022-01-30 12:34 FAILED: patch "[PATCH] x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN" failed to apply to 5.10-stable tree gregkh
@ 2022-01-31 17:16 ` Luck, Tony
2022-01-31 17:35 ` Greg KH
0 siblings, 1 reply; 6+ messages in thread
From: Luck, Tony @ 2022-01-31 17:16 UTC (permalink / raw)
To: gregkh; +Cc: ailin.xu, bp, stable
From 72a73811c4bd53e0ec8284c12180068468d7c733 Mon Sep 17 00:00:00 2001
From: Tony Luck <tony.luck@intel.com>
Date: Mon, 31 Jan 2022 09:00:41 -0800
Subject: [PATCH] x86/cpu: Add Sapphire Rapids and Icelake-D to list of CPUs that support PPIN
commit a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab upstream
commit e464121f2d40eabc7d11823fb26db807ce945df4 upstream
Add Sapphire Rapids and Icelake-D to list of CPUs that support PPIN
Signed-off-by: Tony Luck <tony.luck@intel.com>
---
Failed to backport because the sapphire rapids CPU model number
patch had not been backported. Bundled both together here. But if
that breaks stable rules or scripts, I can redo as two patches one
for each upstream commit.
arch/x86/kernel/cpu/mce/intel.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 2577d7875781..886d4648c9dd 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -486,6 +486,8 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
case INTEL_FAM6_BROADWELL_X:
case INTEL_FAM6_SKYLAKE_X:
case INTEL_FAM6_ICELAKE_X:
+ case INTEL_FAM6_ICELAKE_D:
+ case INTEL_FAM6_SAPPHIRERAPIDS_X:
case INTEL_FAM6_XEON_PHI_KNL:
case INTEL_FAM6_XEON_PHI_KNM:
--
2.31.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: FAILED: patch "[PATCH] x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN" failed to apply to 5.10-stable tree
2022-01-31 17:16 ` Luck, Tony
@ 2022-01-31 17:35 ` Greg KH
2022-01-31 17:43 ` [v5.10 stable PATCH 1/2] x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN Tony Luck
0 siblings, 1 reply; 6+ messages in thread
From: Greg KH @ 2022-01-31 17:35 UTC (permalink / raw)
To: Luck, Tony; +Cc: ailin.xu, bp, stable
On Mon, Jan 31, 2022 at 09:16:24AM -0800, Luck, Tony wrote:
> >From 72a73811c4bd53e0ec8284c12180068468d7c733 Mon Sep 17 00:00:00 2001
> From: Tony Luck <tony.luck@intel.com>
> Date: Mon, 31 Jan 2022 09:00:41 -0800
> Subject: [PATCH] x86/cpu: Add Sapphire Rapids and Icelake-D to list of CPUs that support PPIN
>
> commit a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab upstream
> commit e464121f2d40eabc7d11823fb26db807ce945df4 upstream
>
> Add Sapphire Rapids and Icelake-D to list of CPUs that support PPIN
>
> Signed-off-by: Tony Luck <tony.luck@intel.com>
> ---
>
> Failed to backport because the sapphire rapids CPU model number
> patch had not been backported. Bundled both together here. But if
> that breaks stable rules or scripts, I can redo as two patches one
> for each upstream commit.
Two patches please.
thanks,
greg k-h
^ permalink raw reply [flat|nested] 6+ messages in thread
* [v5.10 stable PATCH 1/2] x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN
2022-01-31 17:35 ` Greg KH
@ 2022-01-31 17:43 ` Tony Luck
2022-01-31 17:43 ` [v5.10 stable PATCH 2/2] x86/cpu: Add Xeon Icelake-D " Tony Luck
0 siblings, 1 reply; 6+ messages in thread
From: Tony Luck @ 2022-01-31 17:43 UTC (permalink / raw)
To: stable; +Cc: Greg Kroah-Hartman, bp, ailin.xu, Tony Luck, Ingo Molnar
commit a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab upstream
New CPU model, same MSRs to control and read the inventory number.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20210319173919.291428-1-tony.luck@intel.com
---
arch/x86/kernel/cpu/mce/intel.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 2577d7875781..7cf08c1f082e 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
case INTEL_FAM6_BROADWELL_X:
case INTEL_FAM6_SKYLAKE_X:
case INTEL_FAM6_ICELAKE_X:
+ case INTEL_FAM6_SAPPHIRERAPIDS_X:
case INTEL_FAM6_XEON_PHI_KNL:
case INTEL_FAM6_XEON_PHI_KNM:
--
2.31.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [v5.10 stable PATCH 2/2] x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN
2022-01-31 17:43 ` [v5.10 stable PATCH 1/2] x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN Tony Luck
@ 2022-01-31 17:43 ` Tony Luck
2022-02-03 18:01 ` Greg Kroah-Hartman
0 siblings, 1 reply; 6+ messages in thread
From: Tony Luck @ 2022-01-31 17:43 UTC (permalink / raw)
To: stable; +Cc: Greg Kroah-Hartman, bp, ailin.xu, Tony Luck
commit e464121f2d40eabc7d11823fb26db807ce945df4 upstream
Missed adding the Icelake-D CPU to the list. It uses the same MSRs
to control and read the inventory number as all the other models.
Fixes: dc6b025de95b ("x86/mce: Add Xeon Icelake to list of CPUs that support PPIN")
Reported-by: Ailin Xu <ailin.xu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220121174743.1875294-2-tony.luck@intel.com
---
arch/x86/kernel/cpu/mce/intel.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 7cf08c1f082e..886d4648c9dd 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
case INTEL_FAM6_BROADWELL_X:
case INTEL_FAM6_SKYLAKE_X:
case INTEL_FAM6_ICELAKE_X:
+ case INTEL_FAM6_ICELAKE_D:
case INTEL_FAM6_SAPPHIRERAPIDS_X:
case INTEL_FAM6_XEON_PHI_KNL:
case INTEL_FAM6_XEON_PHI_KNM:
--
2.31.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [v5.10 stable PATCH 2/2] x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN
2022-01-31 17:43 ` [v5.10 stable PATCH 2/2] x86/cpu: Add Xeon Icelake-D " Tony Luck
@ 2022-02-03 18:01 ` Greg Kroah-Hartman
0 siblings, 0 replies; 6+ messages in thread
From: Greg Kroah-Hartman @ 2022-02-03 18:01 UTC (permalink / raw)
To: Tony Luck; +Cc: stable, bp, ailin.xu
On Mon, Jan 31, 2022 at 09:43:33AM -0800, Tony Luck wrote:
> commit e464121f2d40eabc7d11823fb26db807ce945df4 upstream
>
> Missed adding the Icelake-D CPU to the list. It uses the same MSRs
> to control and read the inventory number as all the other models.
>
> Fixes: dc6b025de95b ("x86/mce: Add Xeon Icelake to list of CPUs that support PPIN")
> Reported-by: Ailin Xu <ailin.xu@intel.com>
> Signed-off-by: Tony Luck <tony.luck@intel.com>
> Signed-off-by: Borislav Petkov <bp@suse.de>
> Cc: <stable@vger.kernel.org>
> Link: https://lore.kernel.org/r/20220121174743.1875294-2-tony.luck@intel.com
> ---
> arch/x86/kernel/cpu/mce/intel.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
> index 7cf08c1f082e..886d4648c9dd 100644
> --- a/arch/x86/kernel/cpu/mce/intel.c
> +++ b/arch/x86/kernel/cpu/mce/intel.c
> @@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
> case INTEL_FAM6_BROADWELL_X:
> case INTEL_FAM6_SKYLAKE_X:
> case INTEL_FAM6_ICELAKE_X:
> + case INTEL_FAM6_ICELAKE_D:
> case INTEL_FAM6_SAPPHIRERAPIDS_X:
> case INTEL_FAM6_XEON_PHI_KNL:
> case INTEL_FAM6_XEON_PHI_KNM:
> --
> 2.31.1
>
Both now queued up, thanks!
greg k-h
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-02-03 18:01 UTC | newest]
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2022-01-30 12:34 FAILED: patch "[PATCH] x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN" failed to apply to 5.10-stable tree gregkh
2022-01-31 17:16 ` Luck, Tony
2022-01-31 17:35 ` Greg KH
2022-01-31 17:43 ` [v5.10 stable PATCH 1/2] x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN Tony Luck
2022-01-31 17:43 ` [v5.10 stable PATCH 2/2] x86/cpu: Add Xeon Icelake-D " Tony Luck
2022-02-03 18:01 ` Greg Kroah-Hartman
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