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From: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org
Subject: Re: [PATCH 2/6] drm/i915: Fix bw atomic check when switching between SAGV vs. no SAGV
Date: Mon, 14 Feb 2022 12:05:36 +0200	[thread overview]
Message-ID: <20220214100536.GB24878@intel.com> (raw)
In-Reply-To: <20220214091811.13725-3-ville.syrjala@linux.intel.com>

On Mon, Feb 14, 2022 at 11:18:07AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> If the only thing that is changing is SAGV vs. no SAGV but
> the number of active planes and the total data rates end up
> unchanged we currently bail out of intel_bw_atomic_check()
> early and forget to actually compute the new WGV point
> mask and thus won't actually enable/disable SAGV as requested.
> This ends up poorly if we end up running with SAGV enabled
> when we shouldn't. Usually ends up in underruns.
> To fix this let's go through the QGV point mask computation
> if anyone else already added the bw state for us.

Haven't been looking this in a while. Despite we have been
looking like few revisions together still some bugs :(

I thought SAGV vs No SAGV can't change if active planes 
or data rate didn't change? Because it means we probably
still have same ddb allocations, which means SAGV state
will just stay the same.

Stan

> 
> Cc: stable@vger.kernel.org
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Fixes: 20f505f22531 ("drm/i915: Restrict qgv points which don't have enough bandwidth.")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 23aa8e06de18..d72ccee7d53b 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -846,6 +846,13 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
>  	if (num_psf_gv_points > 0)
>  		mask |= REG_GENMASK(num_psf_gv_points - 1, 0) << ADLS_PSF_PT_SHIFT;
>  
> +	/*
> +	 * If we already have the bw state then recompute everything
> +	 * even if pipe data_rate / active_planes didn't change.
> +	 * Other things (such as SAGV) may have changed.
> +	 */
> +	new_bw_state = intel_atomic_get_new_bw_state(state);
> +
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>  					    new_crtc_state, i) {
>  		unsigned int old_data_rate =
> -- 
> 2.34.1
> 

  reply	other threads:[~2022-02-14 10:42 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20220214091811.13725-1-ville.syrjala@linux.intel.com>
2022-02-14  9:18 ` [PATCH 1/6] drm/i915: Correctly populate use_sagv_wm for all pipes Ville Syrjala
2022-02-14 10:16   ` Lisovskiy, Stanislav
2022-02-14  9:18 ` [PATCH 2/6] drm/i915: Fix bw atomic check when switching between SAGV vs. no SAGV Ville Syrjala
2022-02-14 10:05   ` Lisovskiy, Stanislav [this message]
2022-02-14 10:24     ` Ville Syrjälä
2022-02-14 17:03       ` Lisovskiy, Stanislav
2022-02-14 20:26         ` Ville Syrjälä
2022-02-15  8:59           ` Lisovskiy, Stanislav
2022-02-15 10:10             ` Ville Syrjälä
2022-02-15 11:02               ` Lisovskiy, Stanislav
2022-02-15 11:26                 ` Ville Syrjälä
2022-02-15 16:33                   ` Lisovskiy, Stanislav
2022-02-15 16:52                     ` Ville Syrjälä
2022-02-15 16:58                       ` [Intel-gfx] " Ville Syrjälä
2022-02-15 19:18                         ` Ville Syrjälä
2022-02-14  9:18 ` [PATCH 3/6] drm/i915: Widen the QGV point mask Ville Syrjala
2022-02-14 17:17   ` Lisovskiy, Stanislav

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