From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1DB9C77B7F for ; Sat, 13 May 2023 07:41:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230483AbjEMHlO (ORCPT ); Sat, 13 May 2023 03:41:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230205AbjEMHlN (ORCPT ); Sat, 13 May 2023 03:41:13 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 497185BA0 for ; Sat, 13 May 2023 00:41:12 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 947C9619C8 for ; Sat, 13 May 2023 07:41:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1FBB1C433EF; Sat, 13 May 2023 07:41:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1683963671; bh=VVBoxifj44nqBN/qVS6ZKK1OT8lDqZk6ckN1fyMmRtw=; h=Subject:To:Cc:From:Date:From; b=wmQWe+DPjDLa2nOfcpXCJ317ea+hItPBcaFjl9qOVc+VDiZc6hM+BVPO56n98Ic2U UllI/ZB8DjvNdbxIOpgkdIVMpaV8NNoTJeNwhPZGtT51L0r7RZs2KtOU7r/Hc77Ob1 T+Ct0cx6oRgunY5rNV1+yBISbc34J9JOfk0mcyLc= Subject: FAILED: patch "[PATCH] drm/amd/display: Remove OTG DIV register write for Virtual" failed to apply to 6.2-stable tree To: SyedSaaem.Rizvi@amd.com, Alvin.Lee2@amd.com, Samson.Tam@amd.com, alexander.deucher@amd.com, daniel.wheeler@amd.com, mario.limonciello@amd.com, qingqing.zhuo@amd.com Cc: From: Date: Sat, 13 May 2023 16:21:16 +0900 Message-ID: <2023051316-overfull-prissy-1fa3@gregkh> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org The patch below does not apply to the 6.2-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.2.y git checkout FETCH_HEAD git cherry-pick -x 5d04d13954479292dd45e38a46dfa31abb8dc2e0 # git commit -s git send-email --to '' --in-reply-to '2023051316-overfull-prissy-1fa3@gregkh' --subject-prefix 'PATCH 6.2.y' HEAD^.. Possible dependencies: 5d04d1395447 ("drm/amd/display: Remove OTG DIV register write for Virtual signals.") 3b214bb7185d ("drm/amd/display: fix k1 k2 divider programming for phantom streams") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ >From 5d04d13954479292dd45e38a46dfa31abb8dc2e0 Mon Sep 17 00:00:00 2001 From: Saaem Rizvi Date: Mon, 27 Feb 2023 18:55:07 -0500 Subject: [PATCH] drm/amd/display: Remove OTG DIV register write for Virtual signals. [WHY] Hot plugging and then hot unplugging leads to k1 and k2 values to change, as signal is detected as a virtual signal on hot unplug. Writing these values to OTG_PIXEL_RATE_DIV register might cause primary display to blank (known hw bug). [HOW] No longer write k1 and k2 values to register if signal is virtual, we have safe guards in place in the case that k1 and k2 is unassigned so that an unknown value is not written to the register either. Cc: stable@vger.kernel.org Cc: Mario Limonciello Reviewed-by: Samson Tam Reviewed-by: Alvin Lee Acked-by: Qingqing Zhuo Signed-off-by: Saaem Rizvi Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c index 5016b1313f3d..f9073b722b36 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@ -1111,7 +1111,7 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign *k2_div = PIXEL_RATE_DIV_BY_2; else *k2_div = PIXEL_RATE_DIV_BY_4; - } else if (dc_is_dp_signal(stream->signal) || dc_is_virtual_signal(stream->signal)) { + } else if (dc_is_dp_signal(stream->signal)) { if (two_pix_per_container) { *k1_div = PIXEL_RATE_DIV_BY_1; *k2_div = PIXEL_RATE_DIV_BY_2;