From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB115C77B7F for ; Sat, 13 May 2023 07:39:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229786AbjEMHjW (ORCPT ); Sat, 13 May 2023 03:39:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229463AbjEMHjU (ORCPT ); Sat, 13 May 2023 03:39:20 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62DB335B5 for ; Sat, 13 May 2023 00:39:19 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id F3AC961827 for ; Sat, 13 May 2023 07:39:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7E704C433EF; Sat, 13 May 2023 07:39:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1683963558; bh=eoYJgGhHXfp6cXkzjnjy4eSyMYqYfN/myyPySAFRzko=; h=Subject:To:Cc:From:Date:From; b=pCdBy+l4d+sLpCMo/mgUSQkXu/oznFXSAmxM7XZcWhZBWJGZ6Qu5MBwEOuv+/OpQm V4F7KKtvIm1aJ94Sefg0N88vVM+DScsFW5P/a+Ww58CIPBhqPl53sSUiWZ9jQDCqo7 ldZwubPsvUNAwmy8Aanu1c1tnEHp8dT6Fvq4ixy4= Subject: FAILED: patch "[PATCH] drm/amd/display: disconnect MPCC only on OTG change" failed to apply to 6.3-stable tree To: ayugupta@amd.com, Alvin.Lee2@amd.com, alexander.deucher@amd.com, daniel.wheeler@amd.com, mario.limonciello@amd.com, qingqing.zhuo@amd.com Cc: From: Date: Sat, 13 May 2023 16:20:24 +0900 Message-ID: <2023051324-underfed-dingy-8ae6@gregkh> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org The patch below does not apply to the 6.3-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.3.y git checkout FETCH_HEAD git cherry-pick -x 562e08223a85f315122cd65e8f99b8c0a42b8771 # git commit -s git send-email --to '' --in-reply-to '2023051324-underfed-dingy-8ae6@gregkh' --subject-prefix 'PATCH 6.3.y' HEAD^.. Possible dependencies: 562e08223a85 ("drm/amd/display: disconnect MPCC only on OTG change") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ >From 562e08223a85f315122cd65e8f99b8c0a42b8771 Mon Sep 17 00:00:00 2001 From: Ayush Gupta Date: Thu, 2 Mar 2023 09:58:05 -0500 Subject: [PATCH] drm/amd/display: disconnect MPCC only on OTG change [Why] Framedrops are observed while playing Vp9 and Av1 10 bit video on 8k resolution using VSR while playback controls are disappeared/appeared [How] Now ODM 2 to 1 is disabled for 5k or greater resolutions on VSR. Cc: stable@vger.kernel.org Cc: Mario Limonciello Reviewed-by: Alvin Lee Acked-by: Qingqing Zhuo Signed-off-by: Ayush Gupta Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c index f6f72e7c9e86..633491331722 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -1914,6 +1914,7 @@ int dcn32_populate_dml_pipes_from_context( struct pipe_ctx *pipe; bool subvp_in_use = false; struct dc_crtc_timing *timing; + bool vsr_odm_support = false; dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); @@ -1931,12 +1932,15 @@ int dcn32_populate_dml_pipes_from_context( timing = &pipe->stream->timing; pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; + vsr_odm_support = (res_ctx->pipe_ctx[i].stream->src.width >= 5120 && + res_ctx->pipe_ctx[i].stream->src.width > res_ctx->pipe_ctx[i].stream->dst.width); if (context->stream_count == 1 && context->stream_status[0].plane_count == 1 && !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) && is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) && pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ && - dc->debug.enable_single_display_2to1_odm_policy) { + dc->debug.enable_single_display_2to1_odm_policy && + !vsr_odm_support) { //excluding 2to1 ODM combine on >= 5k vsr pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; } pipe_cnt++;