From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3595CC77B73 for ; Sat, 27 May 2023 00:32:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230084AbjE0AcT (ORCPT ); Fri, 26 May 2023 20:32:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229901AbjE0AcS (ORCPT ); Fri, 26 May 2023 20:32:18 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82C43F3 for ; Fri, 26 May 2023 17:32:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685147537; x=1716683537; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=WN+VSNBqpt/OhL21osV4BQaYkCJr1yAsrQs36LSYjLM=; b=kZOYRN7HlUigo7nSSPKJB1H7l4oqT/BBLZd3lNOf89DU3LY+63jB0sY/ tXlhebh0gugsvhOLVLozxYKaw81gal7m/raFhGJO5dfoaxu0SOnlsnPRM fIhiMrQbp1I63OhEkis8vvBKJZXYjqVr28s6qYNXnHnXQHbhSJKh68pgy kQXXfY70lg9TvGLEX5mgOxFEjJUuOhULJ0CHyouRVgi99joTpGjpL1clf W4Erqpl7Eif589hUH9iujAtMTEZR1j6d2SXNhfh+roDPlG/PsoYLP8vtF bPK2ZVvyf+d4viXBw4dEnjHtR68gTOo4P7+grPfpBmT525jfklKIz3DrS w==; X-IronPort-AV: E=McAfee;i="6600,9927,10722"; a="354353354" X-IronPort-AV: E=Sophos;i="6.00,195,1681196400"; d="scan'208";a="354353354" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2023 17:32:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10722"; a="775252910" X-IronPort-AV: E=Sophos;i="6.00,195,1681196400"; d="scan'208";a="775252910" Received: from jaleon-mobl.amr.corp.intel.com (HELO dsneddon-desk.sneddon.lan) ([10.212.73.60]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2023 17:32:17 -0700 From: Daniel Sneddon To: stable@vger.kernel.org, dave.hansen@linux.intel.com, tglx@linutronix.de Subject: [PATCH 5.10.y] x86/mm: Avoid incomplete Global INVLPG flushes Date: Fri, 26 May 2023 17:32:12 -0700 Message-Id: <20230527003212.1260724-1-daniel.sneddon@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <2023052613-galore-flame-b5de@gregkh> References: <2023052613-galore-flame-b5de@gregkh> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Dave Hansen The INVLPG instruction is used to invalidate TLB entries for a specified virtual address. When PCIDs are enabled, INVLPG is supposed to invalidate TLB entries for the specified address for both the current PCID *and* Global entries. (Note: Only kernel mappings set Global=1.) Unfortunately, some INVLPG implementations can leave Global translations unflushed when PCIDs are enabled. As a workaround, never enable PCIDs on affected processors. I expect there to eventually be microcode mitigations to replace this software workaround. However, the exact version numbers where that will happen are not known today. Once the version numbers are set in stone, the processor list can be tweaked to only disable PCIDs on affected processors with affected microcode. Note: if anyone wants a quick fix that doesn't require patching, just stick 'nopcid' on your kernel command-line. Signed-off-by: Dave Hansen Reviewed-by: Thomas Gleixner Cc: stable@vger.kernel.org (cherry picked from commit ce0b15d11ad837fbacc5356941712218e38a0a83) Signed-off-by: Daniel Sneddon --- arch/x86/include/asm/intel-family.h | 5 +++++ arch/x86/mm/init.c | 25 +++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 9abe842dbd843..14b52718917f6 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -98,6 +98,11 @@ #define INTEL_FAM6_LAKEFIELD 0x8A #define INTEL_FAM6_ALDERLAKE 0x97 #define INTEL_FAM6_ALDERLAKE_L 0x9A +#define INTEL_FAM6_ALDERLAKE_N 0xBE + +#define INTEL_FAM6_RAPTORLAKE 0xB7 +#define INTEL_FAM6_RAPTORLAKE_P 0xBA +#define INTEL_FAM6_RAPTORLAKE_S 0xBF /* "Small Core" Processors (Atom) */ diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 63d8c6c7d1254..ff3b0d8fe0486 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -254,6 +255,24 @@ static void __init probe_page_size_mask(void) } } +#define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \ + .family = 6, \ + .model = _model, \ + } +/* + * INVLPG may not properly flush Global entries + * on these CPUs when PCIDs are enabled. + */ +static const struct x86_cpu_id invlpg_miss_ids[] = { + INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), + INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), + INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), + {} +}; + static void setup_pcid(void) { if (!IS_ENABLED(CONFIG_X86_64)) @@ -262,6 +281,12 @@ static void setup_pcid(void) if (!boot_cpu_has(X86_FEATURE_PCID)) return; + if (x86_match_cpu(invlpg_miss_ids)) { + pr_info("Incomplete global flushes, disabling PCID"); + setup_clear_cpu_cap(X86_FEATURE_PCID); + return; + } + if (boot_cpu_has(X86_FEATURE_PGE)) { /* * This can't be cr4_set_bits_and_update_boot() -- the -- 2.25.1