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Date:   Sun, 28 May 2023 08:39:30 +0100
From:   Greg KH <gregkh@linuxfoundation.org>
To:     Daniel Sneddon <daniel.sneddon@linux.intel.com>
Cc:     stable@vger.kernel.org, dave.hansen@linux.intel.com,
        tglx@linutronix.de
Subject: Re: [PATCH 5.15.y] x86/mm: Avoid incomplete Global INVLPG flushes
Message-ID: <2023052820-lilac-email-41e1@gregkh>
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 <20230527001834.1208927-1-daniel.sneddon@linux.intel.com>
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On Fri, May 26, 2023 at 05:18:34PM -0700, Daniel Sneddon wrote:
> From: Dave Hansen <dave.hansen@linux.intel.com>
> 
> The INVLPG instruction is used to invalidate TLB entries for a
> specified virtual address.  When PCIDs are enabled, INVLPG is supposed
> to invalidate TLB entries for the specified address for both the
> current PCID *and* Global entries.  (Note: Only kernel mappings set
> Global=1.)
> 
> Unfortunately, some INVLPG implementations can leave Global
> translations unflushed when PCIDs are enabled.
> 
> As a workaround, never enable PCIDs on affected processors.
> 
> I expect there to eventually be microcode mitigations to replace this
> software workaround.  However, the exact version numbers where that
> will happen are not known today.  Once the version numbers are set in
> stone, the processor list can be tweaked to only disable PCIDs on
> affected processors with affected microcode.
> 
> Note: if anyone wants a quick fix that doesn't require patching, just
> stick 'nopcid' on your kernel command-line.
> 
> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
> Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
> Cc: stable@vger.kernel.org
> (cherry picked from commit ce0b15d11ad837fbacc5356941712218e38a0a83)
> Signed-off-by: Daniel Sneddon <daniel.sneddon@linux.intel.com>
> ---
>  arch/x86/include/asm/intel-family.h |  5 +++++
>  arch/x86/mm/init.c                  | 25 +++++++++++++++++++++++++
>  2 files changed, 30 insertions(+)

All now queued up, thanks.

greg k-h