From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C219FEB64DA for ; Thu, 20 Jul 2023 21:08:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230040AbjGTVIx (ORCPT ); Thu, 20 Jul 2023 17:08:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229484AbjGTVIx (ORCPT ); Thu, 20 Jul 2023 17:08:53 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FFD01BC1 for ; Thu, 20 Jul 2023 14:08:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689887332; x=1721423332; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1EoYKC9OsCTE8FBOzuj74SARGZf9U7AsAFTMuvBNgs0=; b=i0U+bzukZ/n1ZI4DEN2fWAPhJykCmDxSiDTVjC+wc7fjT+92Soo5j09E +vdbFHViRaHH+6sCPtl1oeX1lS/UOmctNMo/erbSYoEw6QfQr+FllsduD ofpwfM+xAgamN3VfkOAn8AcXAvLwWxLtp/MN0nnSb5HQcEawaKkNr3iLl r55+0VNccGHYbCSQ8uNpaRCo21RiAK3qL+5DtNT8x9eyEEsffv9YctQtd 6pbtYdg4jEXvBqcFi0eqeROvRUa5a5iU3E1ajX739CcCy0jdZ5PbyJ8/K vMSvMav0dfGOEIYVFFU9zaxRQW5YsvW3MdV/Qiigln5WrboLi9eHthlNj A==; X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="347167431" X-IronPort-AV: E=Sophos;i="6.01,219,1684825200"; d="scan'208";a="347167431" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2023 14:08:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="754177987" X-IronPort-AV: E=Sophos;i="6.01,219,1684825200"; d="scan'208";a="754177987" Received: from sdene1-mobl1.ger.corp.intel.com (HELO intel.com) ([10.252.32.238]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2023 14:08:32 -0700 From: Andi Shyti To: Jonathan Cavitt , Matt Roper , Chris Wilson , Mika Kuoppala , Nirmoy Das , Andrzej Hajda Cc: intel-gfx , dri-evel , linux-stable , Andi Shyti Subject: [PATCH v7 7/9] drm/i915/gt: Ensure memory quiesced before invalidation for all engines Date: Thu, 20 Jul 2023 23:07:35 +0200 Message-Id: <20230720210737.761400-8-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230720210737.761400-1-andi.shyti@linux.intel.com> References: <20230720210737.761400-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Commit af9e423a8aae ("drm/i915/gt: Ensure memory quiesced before invalidation") has made sure that the memory is quiesced before invalidating the AUX CCS table. Do it for all the other engines and not just RCS. Signed-off-by: Andi Shyti Cc: Jonathan Cavitt Cc: Matt Roper Cc: # v5.8+ --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 36 ++++++++++++++++-------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index 202d6ff8b5264..b6dd22eb2d9b2 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -316,26 +316,40 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) { intel_engine_mask_t aux_inv = 0; - u32 cmd, *cs; + u32 cmd_flush = 0; + u32 cmd = 4; + u32 *cs; - cmd = 4; - if (mode & EMIT_INVALIDATE) { + if (mode & EMIT_INVALIDATE) cmd += 2; - if (HAS_AUX_CCS(rq->engine->i915) && - (rq->engine->class == VIDEO_DECODE_CLASS || - rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) { - aux_inv = rq->engine->mask & - ~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0); - if (aux_inv) - cmd += 4; - } + if (HAS_AUX_CCS(rq->engine->i915)) + aux_inv = rq->engine->mask & + ~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0); + + /* + * On Aux CCS platforms the invalidation of the Aux + * table requires quiescing memory traffic beforehand + */ + if (aux_inv) { + cmd += 4; /* for the AUX invalidation */ + cmd += 2; /* for the engine quiescing */ + + cmd_flush = MI_FLUSH_DW; + + if (rq->engine->class == COPY_ENGINE_CLASS) + cmd_flush |= MI_FLUSH_DW_CCS; } cs = intel_ring_begin(rq, cmd); if (IS_ERR(cs)) return PTR_ERR(cs); + if (cmd_flush) { + *cs++ = cmd_flush; + *cs++ = 0; + } + if (mode & EMIT_INVALIDATE) *cs++ = preparser_disable(true); -- 2.40.1