From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C4CAEEB566 for ; Fri, 8 Sep 2023 19:32:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234101AbjIHTcd (ORCPT ); Fri, 8 Sep 2023 15:32:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234716AbjIHTcd (ORCPT ); Fri, 8 Sep 2023 15:32:33 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C99019B5; Fri, 8 Sep 2023 12:32:08 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D6997C433D9; Fri, 8 Sep 2023 19:31:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1694201487; bh=UtXPPDzp/BTiZR0qZBQsbPCE0DChlHRJw03YA8zf+8Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l8VYtTomeaLjNrNBJIpjZsIp8WsyCiFb93Reew3XqCoarivgGx1gItZfdKWVjeK+P S3d7D6/my8DHpHVr1orvy5FU6ulQUyjl+WKmxpqHCbcquM8wKkw3tUY5v5yxajBEcd 8dI4gfi1u5VAwFqde6Clh0HWF3Hkb1aZAG7kP39O8J0td4AYWp3c2y415NrWVFZDJD werLGoF6WT+3bYt/RpIw+QHDRFjd2g7d0Bomddw6YGRaGbyF6sr+G5KhucM2wggvUV zM4Dg/mxtF1gq5y+z/JrOTmmZD1YvmmSm+gqkH307AbWSPajzUyMhl5zGlZt1+6CFD NIQrrc2m0Ncgg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Rob Clark , Konrad Dybcio , Dmitry Baryshkov , Sasha Levin , robdclark@gmail.com, quic_abhinavk@quicinc.com, airlied@gmail.com, daniel@ffwll.ch, johan+linaro@kernel.org, quic_akhilpo@quicinc.com, andersson@kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH AUTOSEL 6.5 25/36] drm/msm/adreno: Use quirk to identify cached-coherent support Date: Fri, 8 Sep 2023 15:28:36 -0400 Message-Id: <20230908192848.3462476-25-sashal@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230908192848.3462476-1-sashal@kernel.org> References: <20230908192848.3462476-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.5.2 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Rob Clark [ Upstream commit 155668ef412fc82ff3172666831d95770141cdd6 ] It is better to explicitly list it. With the move to opaque chip-id's for future devices, we should avoid trying to infer things like generation from the numerical value. Signed-off-by: Rob Clark Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549765/ Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +++++++++++++++------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 5751077c201eb..715ec4139b626 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -275,6 +275,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), @@ -286,6 +287,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .hwcg = a615_hwcg, @@ -299,6 +301,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a630_zap.mdt", .hwcg = a630_hwcg, @@ -312,6 +315,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg, @@ -325,7 +329,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", .hwcg = a650_hwcg, @@ -340,7 +345,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", .hwcg = a660_hwcg, @@ -353,7 +359,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .hwcg = a660_hwcg, .address_space_size = SZ_16G, @@ -367,6 +374,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_2M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg, @@ -378,7 +386,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_4M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", .hwcg = a690_hwcg, @@ -590,9 +599,9 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) if (ret) return ret; - if (config.rev.core >= 6) - if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu))) - priv->has_cached_coherent = true; + priv->has_cached_coherent = + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) && + !adreno_has_gmu_wrapper(to_adreno_gpu(gpu)); return 0; } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index a925e04a2283c..129771563f3fd 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -33,6 +33,7 @@ enum { #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) +#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) struct adreno_rev { uint8_t core; -- 2.40.1