From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9A60E95A96 for ; Mon, 9 Oct 2023 13:51:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377372AbjJINva (ORCPT ); Mon, 9 Oct 2023 09:51:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377400AbjJINv3 (ORCPT ); Mon, 9 Oct 2023 09:51:29 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02F6791 for ; Mon, 9 Oct 2023 06:51:28 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3E9CDC433C7; Mon, 9 Oct 2023 13:51:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1696859487; bh=+ui6RtB3LWhI/+B1hbbTMZJQR0BWco+o6F3DNZPvyzY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DKXhcQDPv3e4viyxC5dZCaNOZ2JfdxTTB4Qa+KCju0dcL4My68qm6nfMFAJGfMLxL mfpCp8rlIC9x+XG3roo3ztc6hq+ASGgPGlPk3IBEKpDTL2gLytWo/0uU45quQhAa+A vOjJ/bRMG7co8D5Y2QmqGopocUp6jFLzT+Rgn7Ow= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Jie Wang , Jijie Shao , Paolo Abeni , Sasha Levin Subject: [PATCH 4.19 09/91] net: hns3: add 5ms delay before clear firmware reset irq source Date: Mon, 9 Oct 2023 15:05:41 +0200 Message-ID: <20231009130111.856960240@linuxfoundation.org> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231009130111.518916887@linuxfoundation.org> References: <20231009130111.518916887@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org 4.19-stable review patch. If anyone has any objections, please let me know. ------------------ From: Jie Wang [ Upstream commit 0770063096d5da4a8e467b6e73c1646a75589628 ] Currently the reset process in hns3 and firmware watchdog init process is asynchronous. we think firmware watchdog initialization is completed before hns3 clear the firmware interrupt source. However, firmware initialization may not complete early. so we add delay before hns3 clear firmware interrupt source and 5 ms delay is enough to avoid second firmware reset interrupt. Fixes: c1a81619d73a ("net: hns3: Add mailbox interrupt handling to PF driver") Signed-off-by: Jie Wang Signed-off-by: Jijie Shao Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index 2c334b56fd42c..d668d25ae7e76 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -2517,8 +2517,13 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, u32 regclr) { +#define HCLGE_IMP_RESET_DELAY 5 + switch (event_type) { case HCLGE_VECTOR0_EVENT_RST: + if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) + mdelay(HCLGE_IMP_RESET_DELAY); + hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); break; case HCLGE_VECTOR0_EVENT_MBX: -- 2.40.1