From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44734C001B5 for ; Mon, 6 Nov 2023 23:14:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233527AbjKFXO6 (ORCPT ); Mon, 6 Nov 2023 18:14:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233461AbjKFXOx (ORCPT ); Mon, 6 Nov 2023 18:14:53 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 028BC118; Mon, 6 Nov 2023 15:14:51 -0800 (PST) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A0545C433C7; Mon, 6 Nov 2023 23:14:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699312490; bh=2VpchQM44d7HzgCX3wgizYzX0JgaRvK/XXJiO68xAFE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rVIHLf3evQsBBuXUyyuFq6ZzQ4Yh8RC+2fSk4PAMUMr9EDgthbqax2eYisiJPk8ro E9sEX9kAzow6MXm2ImdsKF2p1akQQ/lAyjO+4gQONGBIFCKfaiH5vmWV+zl+7FdgtZ pGhdaVOMh44AQDR/w0/N+Yplu2TVarURMq9/2of7WUn7GJss0f2ZnXe/SzG+6thom1 V/AKLtCi0ndZdSgEA8cmIeWHhXmVeHS6tMLJUWQrpp5ec56h5J7bZTd7ju3F5eRIbS YS62R5HCpsgU+tJJ2O7wDMlbo13BYJBPrDKGkM7KRTUDXxziN2zo/BW2TE3QFjso8l 9b/ZT81pismow== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Ronald Wahl , Alexandre Belloni , Daniel Lezcano , Sasha Levin , tglx@linutronix.de, nicolas.ferre@microchip.com, claudiu.beznea@tuxon.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 6.6 08/13] clocksource/drivers/timer-atmel-tcb: Fix initialization on SAM9 hardware Date: Mon, 6 Nov 2023 18:14:21 -0500 Message-ID: <20231106231435.3734790-8-sashal@kernel.org> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231106231435.3734790-1-sashal@kernel.org> References: <20231106231435.3734790-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.6 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Ronald Wahl [ Upstream commit 6d3bc4c02d59996d1d3180d8ed409a9d7d5900e0 ] On SAM9 hardware two cascaded 16 bit timers are used to form a 32 bit high resolution timer that is used as scheduler clock when the kernel has been configured that way (CONFIG_ATMEL_CLOCKSOURCE_TCB). The driver initially triggers a reset-to-zero of the two timers but this reset is only performed on the next rising clock. For the first timer this is ok - it will be in the next 60ns (16MHz clock). For the chained second timer this will only happen after the first timer overflows, i.e. after 2^16 clocks (~4ms with a 16MHz clock). So with other words the scheduler clock resets to 0 after the first 2^16 clock cycles. It looks like that the scheduler does not like this and behaves wrongly over its lifetime, e.g. some tasks are scheduled with a long delay. Why that is and if there are additional requirements for this behaviour has not been further analysed. There is a simple fix for resetting the second timer as well when the first timer is reset and this is to set the ATMEL_TC_ASWTRG_SET bit in the Channel Mode register (CMR) of the first timer. This will also rise the TIOA line (clock input of the second timer) when a software trigger respective SYNC is issued. Signed-off-by: Ronald Wahl Acked-by: Alexandre Belloni Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20231007161803.31342-1-rwahl@gmx.de Signed-off-by: Sasha Levin --- drivers/clocksource/timer-atmel-tcb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c index 27af17c995900..2a90c92a9182a 100644 --- a/drivers/clocksource/timer-atmel-tcb.c +++ b/drivers/clocksource/timer-atmel-tcb.c @@ -315,6 +315,7 @@ static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx) writel(mck_divisor_idx /* likely divide-by-8 */ | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP /* free-run */ + | ATMEL_TC_ASWTRG_SET /* TIOA0 rises at software trigger */ | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */ | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */ tcaddr + ATMEL_TC_REG(0, CMR)); -- 2.42.0