Re: [PATCH 6.1 000/366] 6.1.64-rc4 review

[Conor Dooley <conor.dooley@microchip.com>]

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On Sun, Nov 26, 2023 at 03:46:28PM +0000, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 6.1.64 release.
> There are 366 patches in this series, all will be posted as a response
> to this one.  If anyone has any issues with these being applied, please
> let me know.

I missed testing 6.1.63 so I noticed this only here, but my CI is
complaining about seeing some
[    0.000000] Couldn't find cpu id for hartid [0]
during boot.

It was caused by

commit 3df98bd3196665f2fd37fcc5b2d483a24a314095
Author: Anup Patel <apatel@ventanamicro.com>
Date:   Fri Oct 27 21:12:53 2023 +0530

    RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
    
    [ Upstream commit c4676f8dc1e12e68d6511f9ed89707fdad4c962c ]
    
    The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails
    for HARTs disabled in the DT. This results in the following warning
    thrown by the RISC-V INTC driver for the E-core on SiFive boards:
    
    [    0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller
    
    The riscv_of_parent_hartid() is only expected to read the hartid
    from the DT so we directly call of_get_cpu_hwid() instead of calling
    riscv_of_processor_hartid().
    
    Fixes: ad635e723e17 ("riscv: cpu: Add 64bit hartid support on RV64")
    Signed-off-by: Anup Patel <apatel@ventanamicro.com>
    Reviewed-by: Atish Patra <atishp@rivosinc.com>
    Link: https://lore.kernel.org/r/20231027154254.355853-2-apatel@ventanamicro.com
    Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>

and there is already a fix for this in Linus' tree though that you can
pick:
52909f176802 ("RISC-V: drop error print from riscv_hartid_to_cpuid()")

That's just one error print that realistically has no impact on the
operation of the system, and is not introduced by this particular
version, so

Tested-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

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