From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71D711BDF1; Wed, 3 Jan 2024 17:07:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="V7A1EDhv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E6972C433C9; Wed, 3 Jan 2024 17:07:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1704301654; bh=AGF1V5JPzE/usVsb/nZDcNXtKIBgmGoZn01t0Nvfkbw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V7A1EDhvOSqZcDFr6nTBZChzsyuXDZGKbxx68rXzxPkWIHhIzta/D4Ft0EG3SE8A+ +4wz7lYU3QzNDXzAGnUe2yxRgBJ1Vv/pqRuwVksYNVEgf/GRYABQxkfgwmbVzLx6v4 jX2NBqCzIkmAZnEKQdmCJDh26hgXB2nuYBcj2Fys= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Tony Lindgren Subject: [PATCH 5.15 60/95] bus: ti-sysc: Flush posted write only after srst_udelay Date: Wed, 3 Jan 2024 17:55:08 +0100 Message-ID: <20240103164902.979384486@linuxfoundation.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103164853.921194838@linuxfoundation.org> References: <20240103164853.921194838@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.15-stable review patch. If anyone has any objections, please let me know. ------------------ From: Tony Lindgren commit f71f6ff8c1f682a1cae4e8d7bdeed9d7f76b8f75 upstream. Commit 34539b442b3b ("bus: ti-sysc: Flush posted write on enable before reset") caused a regression reproducable on omap4 duovero where the ISS target module can produce interconnect errors on boot. Turns out the registers are not accessible until after a delay for devices needing a ti,sysc-delay-us value. Let's fix this by flushing the posted write only after the reset delay. We do flushing also for ti,sysc-delay-us using devices as that should trigger an interconnect error if the delay is not properly configured. Let's also add some comments while at it. Fixes: 34539b442b3b ("bus: ti-sysc: Flush posted write on enable before reset") Cc: stable@vger.kernel.org Signed-off-by: Tony Lindgren Signed-off-by: Greg Kroah-Hartman --- drivers/bus/ti-sysc.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -2104,13 +2104,23 @@ static int sysc_reset(struct sysc *ddata sysc_val = sysc_read_sysconfig(ddata); sysc_val |= sysc_mask; sysc_write(ddata, sysc_offset, sysc_val); - /* Flush posted write */ + + /* + * Some devices need a delay before reading registers + * after reset. Presumably a srst_udelay is not needed + * for devices that use a rstctrl register reset. + */ + if (ddata->cfg.srst_udelay) + fsleep(ddata->cfg.srst_udelay); + + /* + * Flush posted write. For devices needing srst_udelay + * this should trigger an interconnect error if the + * srst_udelay value is needed but not configured. + */ sysc_val = sysc_read_sysconfig(ddata); } - if (ddata->cfg.srst_udelay) - fsleep(ddata->cfg.srst_udelay); - if (ddata->post_reset_quirk) ddata->post_reset_quirk(ddata);