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[46.135.65.8]) by smtp.gmail.com with ESMTPSA id u3-20020a05600c00c300b00411ec07674esm1012499wmm.31.2024.02.14.01.29.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Feb 2024 01:29:13 -0800 (PST) Date: Wed, 14 Feb 2024 10:29:11 +0100 From: Andrew Jones To: Samuel Holland Cc: Palmer Dabbelt , linux-kernel@vger.kernel.org, Conor Dooley , linux-riscv@lists.infradead.org, Stefan O'Rear , stable@vger.kernel.org Subject: Re: [PATCH -fixes v3 2/2] riscv: Save/restore envcfg CSR during CPU suspend Message-ID: <20240214-cd40380c3969dc9450f05848@orel> References: <20240214090206.195754-1-samuel.holland@sifive.com> <20240214090206.195754-3-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240214090206.195754-3-samuel.holland@sifive.com> On Wed, Feb 14, 2024 at 01:01:57AM -0800, Samuel Holland wrote: > The value of the [ms]envcfg CSR is lost when entering a nonretentive > idle state, so the CSR must be rewritten when resuming the CPU. > > The [ms]envcfg CSR was added in version 1.12 of the privileged ISA, and > is used by extensions other than Zicboz. However, the kernel currenly > has no way to determine the privileged ISA version. Since Zicboz is the > only in-kernel user of this CSR so far, use it as a proxy for > determining if the CSR is implemented. > > Cc: # v6.7+ > Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") > Signed-off-by: Samuel Holland > --- > > Changes in v3: > - Check for Zicboz instead of the privileged ISA version > > Changes in v2: > - Check for privileged ISA v1.12 instead of the specific CSR > - Use riscv_has_extension_likely() instead of new ALTERNATIVE()s > > arch/riscv/include/asm/suspend.h | 1 + > arch/riscv/kernel/suspend.c | 4 ++++ > 2 files changed, 5 insertions(+) > > diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h > index 02f87867389a..491296a335d0 100644 > --- a/arch/riscv/include/asm/suspend.h > +++ b/arch/riscv/include/asm/suspend.h > @@ -14,6 +14,7 @@ struct suspend_context { > struct pt_regs regs; > /* Saved and restored by high-level functions */ > unsigned long scratch; > + unsigned long envcfg; > unsigned long tvec; > unsigned long ie; > #ifdef CONFIG_MMU > diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c > index 239509367e42..28166006688e 100644 > --- a/arch/riscv/kernel/suspend.c > +++ b/arch/riscv/kernel/suspend.c > @@ -15,6 +15,8 @@ > void suspend_save_csrs(struct suspend_context *context) > { > context->scratch = csr_read(CSR_SCRATCH); > + if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) > + context->envcfg = csr_read(CSR_ENVCFG); > context->tvec = csr_read(CSR_TVEC); > context->ie = csr_read(CSR_IE); > > @@ -36,6 +38,8 @@ void suspend_save_csrs(struct suspend_context *context) > void suspend_restore_csrs(struct suspend_context *context) > { > csr_write(CSR_SCRATCH, context->scratch); > + if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) > + csr_write(CSR_ENVCFG, context->envcfg); > csr_write(CSR_TVEC, context->tvec); > csr_write(CSR_IE, context->ie); > > -- > 2.43.0 > Reviewed-by: Andrew Jones