From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E3D22C1B4 for ; Tue, 20 Feb 2024 14:35:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708439754; cv=none; b=EjT07VV5zRkThEqgbjcYELo4ZJ7VkbRj9lnKLPlqtd0zoINKteY+i4KsqNK3+jYxcaAHuU6R+TnaDn96cn45/+5hU7R8/12gwgnNunVWXY9nTf+k8ngR3LL3acjlCTcx9hVyKHcxDq8wXaltJ3si5U5M2jgmNH8PRA6E3qG9/ww= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708439754; c=relaxed/simple; bh=zpJcCXuNWmNtF8KZ20vlTeGsVr5wKNu+A56o8XHCtbU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=icX5bRuD+x+OR5OS9qNzh4MFMXTaXsa5p94VGFwcXRuLn3ERQQAffl5pMzlja7mDsJdyi26Ktwpp7ZseMj0mkqLcMSJtofRv+4iO+n9Ov7TXUIsjlMJDgdGdJBDL9hZl0Ot6NY+RBDMQRME57fR73TN/4kbKdwwhduWNn79N+0c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ia4wJpN2; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ia4wJpN2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708439754; x=1739975754; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zpJcCXuNWmNtF8KZ20vlTeGsVr5wKNu+A56o8XHCtbU=; b=ia4wJpN20aVYXVJjja1pSpio7ncr5/6ceVkGf76RVKg8k2kVpuEQWzeo ytXPi8IdVncQrFd9vdhFdvDJiOba9PFze1Xh9bmC+rm2ZKJWQIj8iFD89 jVZSwz0ZZafK9iv/fggTpTr+by2hunqjjSsuGqg223HAE0ey5FxK3/lHn xBvd+1Q3p/iIyMfShPzVPa3Vd+2BUjUTo6xWKSFDnBZ5RkAKDdxo27OlS 6h2BG42+oC5HdVar2fJ9WjUtA8gShuz6CeLDs7R9JSAhZdvZfsX1ZRz7N FZVZvGwkbT7ezmxrYVyLbkHhUM3qXMW9q0ydDmbdJpnDyoOi+0zgUY10y A==; X-IronPort-AV: E=McAfee;i="6600,9927,10989"; a="2677055" X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="2677055" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2024 06:35:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="5167948" Received: from alichtma-mobl.ger.corp.intel.com (HELO intel.com) ([10.246.34.74]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2024 06:35:50 -0800 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Joonas Lahtinen , Matt Roper , John Harrison , Tvrtko Ursulin , stable@vger.kernel.org, Andi Shyti , Andi Shyti Subject: [PATCH v2 1/2] drm/i915/gt: Disable HW load balancing for CCS Date: Tue, 20 Feb 2024 15:35:25 +0100 Message-ID: <20240220143526.259109-2-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240220143526.259109-1-andi.shyti@linux.intel.com> References: <20240220143526.259109-1-andi.shyti@linux.intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The hardware should not dynamically balance the load between CCS engines. Wa_14019159160 recommends disabling it across all platforms. Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement") Signed-off-by: Andi Shyti Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Matt Roper Cc: # v6.2+ --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 50962cfd1353..cf709f6c05ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1478,6 +1478,7 @@ #define GEN12_RCU_MODE _MMIO(0x14800) #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) +#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1) #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168) #define CHV_FGT_DISABLE_SS0 (1 << 10) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index d67d44611c28..9126b37186fc 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2988,6 +2988,12 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); } + + /* + * Wa_14019159160: disable the CCS load balancing + * indiscriminately for all the platforms + */ + wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE); } static void -- 2.43.0