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Wed, 21 Feb 2024 03:53:35 -0500 (EST) Date: Wed, 21 Feb 2024 09:53:20 +0100 From: Greg KH To: Easwar Hariharan Cc: stable@vger.kernel.org, Anshuman Khandual , Mark Rutland , Marc Zyngier , Oliver Upton , Will Deacon Subject: Re: [PATCH 5.15.y] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata Message-ID: <2024022112-laziness-alongside-0c87@gregkh> References: <2024021948-flashing-prescribe-3dcf@gregkh> <20240220192816.2842423-1-eahariha@linux.microsoft.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240220192816.2842423-1-eahariha@linux.microsoft.com> On Tue, Feb 20, 2024 at 07:28:16PM +0000, Easwar Hariharan wrote: > commit fb091ff394792c018527b3211bbdfae93ea4ac02 upstream > > Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft > implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore > suffers from all the same errata. > > CC: stable@vger.kernel.org # 5.15+ > Signed-off-by: Easwar Hariharan > Reviewed-by: Anshuman Khandual > Acked-by: Mark Rutland > Acked-by: Marc Zyngier > Reviewed-by: Oliver Upton > Link: https://lore.kernel.org/r/20240214175522.2457857-1-eahariha@linux.microsoft.com > Signed-off-by: Will Deacon > Signed-off-by: Easwar Hariharan > --- > Documentation/arm64/silicon-errata.rst | 7 +++++++ > arch/arm64/include/asm/cputype.h | 4 ++++ > arch/arm64/kernel/cpu_errata.c | 3 +++ > 3 files changed, 14 insertions(+) Both now queued up, thanks. greg k-h