From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B1DC13B2B4; Tue, 27 Feb 2024 14:06:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709042809; cv=none; b=mhL7iE0XHT1Y2CuK7gjpNyjwDHmLoSAcxYkpGSpy8/Z75sBfeNHqo6wbOs7E3BD7JIXP+zDHxei9Ll/TgtbR5mf1pbn9nG4caZZNGCktvHVMzGbz7Qx6OSegBIiijM7FB77Uo4XuYuCsvCgpTWeAEOBRMXiE7GooXg5rt13tmNQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709042809; c=relaxed/simple; bh=H0UDLC83fdJH8Szk1uJlT6tg/2Ivhgrh3YL1kHOgMSU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tcyLmedf3KQwCXuz7wh5OHvpk2o3iQ//CEE+2O+ihCxPiu+J8hNEOWHZSNKJzYiZWvjDnNrwNOfdzuZJywebwcWOpkUoR88lcQNaD9h6kBL8N7vlWvF9ipVTlX39V41sEN86d+KOjW2UeFg9nwa9KgXSvW+idGxcJ5+uUiaFRkk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=RAggJR/L; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="RAggJR/L" Received: by smtp.kernel.org (Postfix) with ESMTPSA id ECB17C433C7; Tue, 27 Feb 2024 14:06:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1709042809; bh=H0UDLC83fdJH8Szk1uJlT6tg/2Ivhgrh3YL1kHOgMSU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RAggJR/LRHPdXbcADGr7NueOscDIHNKZd04ovUhSQxN5F0a2ZP9o2PtbjPr2WLxRs 3xwngf+IQA3ylcqHmEgmZWMv3QlQY7JczesdmUoZNs2rD3kbMKfceaqy4my5aSXalp 8IHkQ71OcPoLI/yhqePRMAkSQXLHXCjIpJ9coYMI= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Stephen Boyd , Dmitry Baryshkov , Konrad Dybcio , Bjorn Andersson , Sasha Levin Subject: [PATCH 5.15 121/245] clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC Date: Tue, 27 Feb 2024 14:25:09 +0100 Message-ID: <20240227131619.157417812@linuxfoundation.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240227131615.098467438@linuxfoundation.org> References: <20240227131615.098467438@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.15-stable review patch. If anyone has any objections, please let me know. ------------------ From: Dmitry Baryshkov [ Upstream commit cb81719e3c1165ef1bc33137dc628f750eed8ea4 ] The gdsc_init() function will rewrite the CLK_DIS_WAIT field while registering the GDSC (writing the value 0x2 by default). This will override the setting done in the driver's probe function. Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe function. Fixes: 453361cdd757 ("clk: qcom: Add graphics clock controller driver for SDM845") Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230201172305.993146-2-dmitry.baryshkov@linaro.org Signed-off-by: Sasha Levin --- drivers/clk/qcom/gpucc-sdm845.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c index 110b54401bc6d..970d7414bdf0e 100644 --- a/drivers/clk/qcom/gpucc-sdm845.c +++ b/drivers/clk/qcom/gpucc-sdm845.c @@ -22,8 +22,6 @@ #define CX_GMU_CBCR_SLEEP_SHIFT 4 #define CX_GMU_CBCR_WAKE_MASK 0xf #define CX_GMU_CBCR_WAKE_SHIFT 8 -#define CLK_DIS_WAIT_SHIFT 12 -#define CLK_DIS_WAIT_MASK (0xf << CLK_DIS_WAIT_SHIFT) enum { P_BI_TCXO, @@ -121,6 +119,7 @@ static struct clk_branch gpu_cc_cxo_clk = { static struct gdsc gpu_cx_gdsc = { .gdscr = 0x106c, .gds_hw_ctrl = 0x1540, + .clk_dis_wait_val = 0x8, .pd = { .name = "gpu_cx_gdsc", }, @@ -193,10 +192,6 @@ static int gpu_cc_sdm845_probe(struct platform_device *pdev) value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT; regmap_update_bits(regmap, 0x1098, mask, value); - /* Configure clk_dis_wait for gpu_cx_gdsc */ - regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK, - 8 << CLK_DIS_WAIT_SHIFT); - return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap); } -- 2.43.0