From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F4EB13AA4C; Tue, 27 Feb 2024 13:54:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709042088; cv=none; b=gPv6wlWBci4cgul4xyMPw370QEbxrC1I5pC6+j05DSwdc1IuyuZY7JALfqYASmf87HyLWAzoZkKMYWXBw0e87Ef8iopxqJD1vY55bKie1D6U7V3XngPS2H8hehK8xPsGFrcxPIketaoIEQzSXS4Yc6TQlIZppLcmt3b0ZjxLYH4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709042088; c=relaxed/simple; bh=8g9igAS6XNbdCE44JYLHdJTnFV3PzUd0YqSZnxnJ4kE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=D6yHD2hIqBI8hCJBqw44OBTw2i4rBLVAey7mi4PcGzTUEmGtrbfLkBMyQw89tWG7Nz9IDBam76opsQY7j50thJVhWhVbKgcqSO1ub0IvO8hykxOzl1eHCwg6BRfJFHzMxKHNz+y1u3G81GqmDIt2JgTxNXiWkuhsBqsCFDXpnF8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=hzL4igmL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="hzL4igmL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94051C433C7; Tue, 27 Feb 2024 13:54:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1709042087; bh=8g9igAS6XNbdCE44JYLHdJTnFV3PzUd0YqSZnxnJ4kE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hzL4igmLht1FS5SAJSFFaOnxttOzhobJoT7l+fU2Z7HBlmJN7E4TWba6QvwwknEvt YMR2pivbYYHgUXI3lsX14ySdYq3125SpdfmUwnEt9zduCx4mhDLjsLQ2gbwsOt2pR2 DScYuaR0Mjoo0azFit+Xc/mS5/wU1yDxolMg7sBk= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Nam Cao , Thomas Gleixner , Palmer Dabbelt , Paul Walmsley , Samuel Holland , Marc Zyngier , Guo Ren , linux-riscv@lists.infradead.org Subject: [PATCH 6.6 174/299] irqchip/sifive-plic: Enable interrupt if needed before EOI Date: Tue, 27 Feb 2024 14:24:45 +0100 Message-ID: <20240227131631.437918244@linuxfoundation.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240227131625.847743063@linuxfoundation.org> References: <20240227131625.847743063@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Nam Cao commit 9c92006b896c767218aabe8947b62026a571cfd0 upstream. RISC-V PLIC cannot "end-of-interrupt" (EOI) disabled interrupts, as explained in the description of Interrupt Completion in the PLIC spec: "The PLIC signals it has completed executing an interrupt handler by writing the interrupt ID it received from the claim to the claim/complete register. The PLIC does not check whether the completion ID is the same as the last claim ID for that target. If the completion ID does not match an interrupt source that *is currently enabled* for the target, the completion is silently ignored." Commit 69ea463021be ("irqchip/sifive-plic: Fixup EOI failed when masked") ensured that EOI is successful by enabling interrupt first, before EOI. Commit a1706a1c5062 ("irqchip/sifive-plic: Separate the enable and mask operations") removed the interrupt enabling code from the previous commit, because it assumes that interrupt should already be enabled at the point of EOI. However, this is incorrect: there is a window after a hart claiming an interrupt and before irq_desc->lock getting acquired, interrupt can be disabled during this window. Thus, EOI can be invoked while the interrupt is disabled, effectively nullify this EOI. This results in the interrupt never gets asserted again, and the device who uses this interrupt appears frozen. Make sure that interrupt is really enabled before EOI. Fixes: a1706a1c5062 ("irqchip/sifive-plic: Separate the enable and mask operations") Signed-off-by: Nam Cao Signed-off-by: Thomas Gleixner Cc: Palmer Dabbelt Cc: Paul Walmsley Cc: Samuel Holland Cc: Marc Zyngier Cc: Guo Ren Cc: linux-riscv@lists.infradead.org Cc: Link: https://lore.kernel.org/r/20240131081933.144512-1-namcao@linutronix.de Signed-off-by: Greg Kroah-Hartman --- drivers/irqchip/irq-sifive-plic.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -148,7 +148,13 @@ static void plic_irq_eoi(struct irq_data { struct plic_handler *handler = this_cpu_ptr(&plic_handlers); - writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); + if (unlikely(irqd_irq_disabled(d))) { + plic_toggle(handler, d->hwirq, 1); + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); + plic_toggle(handler, d->hwirq, 0); + } else { + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); + } } #ifdef CONFIG_SMP