From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C67A13B2A7; Tue, 27 Feb 2024 13:32:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709040722; cv=none; b=FtzuLn+K0qFY13yEhJtpcP4PvihKmjbIteF/KapBj8I3cOtJN3MlwUOFDXE2RjuZAIGmzUmXc0mVxn2IbL5g5P+lAQOrAkTWJcA0eYkPqbg6i0i2iyjXAJ+YPiOX3aYNusficR55urxQnKB6iOQ6Y9LiRzPnE/FFOJPaLfhi8jo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709040722; c=relaxed/simple; bh=HFxPnuBSmN2M8zLid3izKvhjKieRQKmCjEradV4I2UA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FNkqLD3m4w7cuYIlxH15PM0C0qFGBVuQErzpxdw2VoeoY9MBYmPW1ACY6uGWjypC2pGr+bAAh8lO/5dsN6Gfxx/i5Eyok8CZG+3OQVXZd6oUY/0qExflISr43SYR787UnymCcqOowvYD6za8IUiMiTNdjoihD28wwklhNynPSKo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=yKb9Auuo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="yKb9Auuo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 968CCC433F1; Tue, 27 Feb 2024 13:32:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1709040722; bh=HFxPnuBSmN2M8zLid3izKvhjKieRQKmCjEradV4I2UA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=yKb9Auuo+ZGNdtxzYltx1vKXq7yuhRyvE5tM8GEZud2HWwg6yMMaq0AOwfrden2S6 XEyS2nUiGqyezTvrmnB2jDe4vaSbIWNUI425r8/b9EdEyC4bstmQpLqfd/75+kfoRi CylpJyHCgslVPtqumU176n5rQAbjSY1IWi1VGwoM= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Chaitanya Dhere , Alvin Lee , Tom Chung , Sohaib Nadeem , Daniel Wheeler , Alex Deucher , Sasha Levin Subject: [PATCH 6.7 057/334] drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz Date: Tue, 27 Feb 2024 14:18:35 +0100 Message-ID: <20240227131632.407821252@linuxfoundation.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240227131630.636392135@linuxfoundation.org> References: <20240227131630.636392135@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.7-stable review patch. If anyone has any objections, please let me know. ------------------ From: Sohaib Nadeem [ Upstream commit 2ff33c759a4247c84ec0b7815f1f223e155ba82a ] [why] Originally, PMFW said min FCLK is 300Mhz, but min DCFCLK can be increased to 400Mhz because min FCLK is now 600Mhz so FCLK >= 1.5 * DCFCLK hardware requirement will still be satisfied. Increasing min DCFCLK addresses underflow issues (underflow occurs when phantom pipe is turned on for some Sub-Viewport configs). [how] Increasing DCFCLK by raising the min_dcfclk_mhz Reviewed-by: Chaitanya Dhere Reviewed-by: Alvin Lee Acked-by: Tom Chung Signed-off-by: Sohaib Nadeem Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index fe2b67d745f0d..3386eb4150fc6 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -2719,7 +2719,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk struct _vcs_dpi_voltage_scaling_st entry = {0}; struct clk_limit_table_entry max_clk_data = {0}; - unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299; + unsigned int min_dcfclk_mhz = 399, min_fclk_mhz = 599; static const unsigned int num_dcfclk_stas = 5; unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; -- 2.43.0