From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 729A47580D; Thu, 29 Feb 2024 15:49:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709221792; cv=none; b=f7hccZsG1TdWD8aC1jaRf8Pp1W8S9XAzBJOc3VJN/uvfVTKmf5BZ3uRl4zuhCr9ieqdPjaa1HilrQ/0e1fojRdlOG+/938KtHAtbkvUUG68Cmw1gR2Aa/Iz/eWg4o+5Z0wFJFT0r/OcjcI6L38lmk5s4mvmhz+3gFJLBmNyYRe8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709221792; c=relaxed/simple; bh=9rAub/AT11/jIi5X3yn6EW32jwa3A2xARBjtsu2qsUQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oiEW+kVl8zPpv9GkmnbfmtjCeEcVt1E6ReGdiVeFTBdvvk0LQDBmNM9zqIaZNlAmb6WahzF49dsze2arvCnvWc9WlJEwFdBI2ol84M031zNEepPeJeeHEw0tgj1UldN/Wm/cc5PmrInF4DWC665kxw3Lbr532Dh1lSIearKvGe4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QHEAFsis; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QHEAFsis" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8C9FBC43394; Thu, 29 Feb 2024 15:49:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1709221792; bh=9rAub/AT11/jIi5X3yn6EW32jwa3A2xARBjtsu2qsUQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QHEAFsisVibUfjxzKDXGs1NsZk81ZiLc5xhJcUeUQSYm8NuVUmoyYQ6WRYvwWwF+t s4SVpmdl4L9gZiW6I804HHbOTrYhAul1mp4B4RExPldZ4nBgASmn9rXY5rdwD7kps0 J0qrUimwKxPAn+lfk0ftkzbteJ6yhq/nMhGZmeakx2uBPlO1tO24BZJYexEomGayRQ QQPAh/4JFvkcSHoiQkSDr6bsvmBZB3Qjl+bXpRXruQ9lSCuG8VkGW1A4Rg2jrqi1Xg E+K4gvHTOAplYpu1JorXnR8RR5Byx4z4ujwhCj8j5JVd1+Qxyo8uF6TShO8L2OedLP FXhluh5165Lvg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Rob Clark , Sasha Levin , robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, airlied@gmail.com, daniel@ffwll.ch, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH AUTOSEL 6.6 03/21] Revert "drm/msm/gpu: Push gpu lock down past runpm" Date: Thu, 29 Feb 2024 10:49:23 -0500 Message-ID: <20240229154946.2850012-3-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240229154946.2850012-1-sashal@kernel.org> References: <20240229154946.2850012-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.6.18 Content-Transfer-Encoding: 8bit From: Rob Clark [ Upstream commit 917e9b7c2350e3e53162fcf5035e5f2d68e2cbed ] This reverts commit abe2023b4cea192ab266b351fd38dc9dbd846df0. Changing the locking order means that scheduler/msm_job_run() can race with the recovery kthread worker, with the result that the GPU gets an extra runpm get when we are trying to power it off. Leaving the GPU in an unrecovered state. I'll need to come up with a different scheme for appeasing lockdep. Signed-off-by: Rob Clark Patchwork: https://patchwork.freedesktop.org/patch/573835/ Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/msm_gpu.c | 11 +++++------ drivers/gpu/drm/msm/msm_ringbuffer.c | 7 +++++-- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 7f64c66673002..5c10b559a5957 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -749,12 +749,14 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) struct msm_ringbuffer *ring = submit->ring; unsigned long flags; - pm_runtime_get_sync(&gpu->pdev->dev); + WARN_ON(!mutex_is_locked(&gpu->lock)); - mutex_lock(&gpu->lock); + pm_runtime_get_sync(&gpu->pdev->dev); msm_gpu_hw_init(gpu); + submit->seqno = submit->hw_fence->seqno; + update_sw_cntrs(gpu); /* @@ -779,11 +781,8 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) gpu->funcs->submit(gpu, submit); gpu->cur_ctx_seqno = submit->queue->ctx->seqno; - hangcheck_timer_reset(gpu); - - mutex_unlock(&gpu->lock); - pm_runtime_put(&gpu->pdev->dev); + hangcheck_timer_reset(gpu); } /* diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c index 40c0bc35a44ce..7f5e0a961bba7 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.c +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c @@ -21,8 +21,6 @@ static struct dma_fence *msm_job_run(struct drm_sched_job *job) msm_fence_init(submit->hw_fence, fctx); - submit->seqno = submit->hw_fence->seqno; - mutex_lock(&priv->lru.lock); for (i = 0; i < submit->nr_bos; i++) { @@ -34,8 +32,13 @@ static struct dma_fence *msm_job_run(struct drm_sched_job *job) mutex_unlock(&priv->lru.lock); + /* TODO move submit path over to using a per-ring lock.. */ + mutex_lock(&gpu->lock); + msm_gpu_submit(gpu, submit); + mutex_unlock(&gpu->lock); + return dma_fence_get(submit->hw_fence); } -- 2.43.0