From: Andi Shyti <andi.shyti@linux.intel.com>
To: intel-gfx <intel-gfx@lists.freedesktop.org>,
dri-devel <dri-devel@lists.freedesktop.org>
Cc: Chris Wilson <chris.p.wilson@linux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
Matt Roper <matthew.d.roper@intel.com>,
John Harrison <John.C.Harrison@Intel.com>,
stable@vger.kernel.org, Andi Shyti <andi.shyti@linux.intel.com>,
Andi Shyti <andi.shyti@kernel.org>,
Tvrtko Ursulin <tursulin@ursulin.net>
Subject: [PATCH v5 3/4] drm/i915/gt: Disable tests for CCS engines beyond the first
Date: Fri, 8 Mar 2024 21:22:18 +0100 [thread overview]
Message-ID: <20240308202223.406384-4-andi.shyti@linux.intel.com> (raw)
In-Reply-To: <20240308202223.406384-1-andi.shyti@linux.intel.com>
In anticipation of the upcoming commit that will operate with
only one CCS stream, when more than one CCS slice is present,
create a new for_each_available_engine() that excludes CCS
engines beyond the forst. Begin using it in the hangcheck
selftest.
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.h | 13 ++++++++++++
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 22 ++++++++++----------
2 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 6e7cab60834c..d3ee7aee9c7c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -188,6 +188,19 @@ void intel_gt_release_all(struct drm_i915_private *i915);
(id__)++) \
for_each_if ((engine__) = (gt__)->engine[(id__)])
+/*
+ * Simple iterator over all initialised engines that
+ * takes into account CCS fixed mode load balancing
+ */
+#define for_each_available_engine(engine__, gt__, id__) \
+ for ((id__) = 0; \
+ (id__) < I915_NUM_ENGINES; \
+ (id__)++) \
+ for_each_if \
+ (((engine__) = (gt__)->engine[(id__)]) && \
+ !(engine__->class == COMPUTE_CLASS && \
+ engine__->instance))
+
/* Iterator over subset of engines selected by mask */
#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 9ce8ff1c04fe..f1e684987ddb 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -296,7 +296,7 @@ static int igt_hang_sanitycheck(void *arg)
if (err)
return err;
- for_each_engine(engine, gt, id) {
+ for_each_available_engine(engine, gt, id) {
struct intel_wedge_me w;
long timeout;
@@ -360,7 +360,7 @@ static int igt_reset_nop(void *arg)
reset_count = i915_reset_count(global);
count = 0;
do {
- for_each_engine(engine, gt, id) {
+ for_each_available_engine(engine, gt, id) {
struct intel_context *ce;
int i;
@@ -433,7 +433,7 @@ static int igt_reset_nop_engine(void *arg)
if (!intel_has_reset_engine(gt))
return 0;
- for_each_engine(engine, gt, id) {
+ for_each_available_engine(engine, gt, id) {
unsigned int reset_count, reset_engine_count, count;
struct intel_context *ce;
IGT_TIMEOUT(end_time);
@@ -553,7 +553,7 @@ static int igt_reset_fail_engine(void *arg)
if (!intel_has_reset_engine(gt))
return 0;
- for_each_engine(engine, gt, id) {
+ for_each_available_engine(engine, gt, id) {
unsigned int count;
struct intel_context *ce;
IGT_TIMEOUT(end_time);
@@ -700,7 +700,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active)
return err;
}
- for_each_engine(engine, gt, id) {
+ for_each_available_engine(engine, gt, id) {
unsigned int reset_count, reset_engine_count;
unsigned long count;
bool using_guc = intel_engine_uses_guc(engine);
@@ -990,7 +990,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
if (!threads)
return -ENOMEM;
- for_each_engine(engine, gt, id) {
+ for_each_available_engine(engine, gt, id) {
unsigned long device = i915_reset_count(global);
unsigned long count = 0, reported;
bool using_guc = intel_engine_uses_guc(engine);
@@ -1010,7 +1010,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
}
memset(threads, 0, sizeof(*threads) * I915_NUM_ENGINES);
- for_each_engine(other, gt, tmp) {
+ for_each_available_engine(other, gt, tmp) {
struct kthread_worker *worker;
threads[tmp].resets =
@@ -1185,7 +1185,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
}
unwind:
- for_each_engine(other, gt, tmp) {
+ for_each_available_engine(other, gt, tmp) {
int ret;
if (!threads[tmp].worker)
@@ -1621,7 +1621,7 @@ static int wait_for_others(struct intel_gt *gt,
struct intel_engine_cs *engine;
enum intel_engine_id id;
- for_each_engine(engine, gt, id) {
+ for_each_available_engine(engine, gt, id) {
if (engine == exclude)
continue;
@@ -1649,7 +1649,7 @@ static int igt_reset_queue(void *arg)
if (err)
goto unlock;
- for_each_engine(engine, gt, id) {
+ for_each_available_engine(engine, gt, id) {
struct intel_selftest_saved_policy saved;
struct i915_request *prev;
IGT_TIMEOUT(end_time);
@@ -1982,7 +1982,7 @@ static int igt_reset_engines_atomic(void *arg)
struct intel_engine_cs *engine;
enum intel_engine_id id;
- for_each_engine(engine, gt, id) {
+ for_each_available_engine(engine, gt, id) {
err = igt_atomic_reset_engine(engine, p);
if (err)
goto out;
--
2.43.0
next prev parent reply other threads:[~2024-03-08 20:23 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-08 20:22 [PATCH v5 0/4] Disable automatic load CCS load balancing Andi Shyti
2024-03-08 20:22 ` [PATCH v5 1/4] drm/i915/gt: Disable HW load balancing for CCS Andi Shyti
2024-03-12 16:58 ` Matt Roper
2024-03-12 20:37 ` Andi Shyti
2024-03-08 20:22 ` [PATCH v5 2/4] drm/i915/gt: Refactor uabi engine class/instance list creation Andi Shyti
2024-03-12 17:08 ` Matt Roper
2024-03-12 20:49 ` Andi Shyti
2024-03-08 20:22 ` Andi Shyti [this message]
2024-03-08 20:25 ` [PATCH v5 3/4] drm/i915/gt: Disable tests for CCS engines beyond the first kernel test robot
2024-03-08 20:22 ` [PATCH v5 4/4] drm/i915/gt: Enable only one CCS for compute workload Andi Shyti
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