From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B261B47A7A; Mon, 1 Apr 2024 15:54:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711986850; cv=none; b=FmmUckksUvzr3FWEs8h/TtPPyydH4ZBevy6U3D/dSp/EYOQQBWK0fDzxAy98COnR7udqHf3i8d0tA5trnLCTDbtk9xOO/xrr7MrUpLBWPZxVEcQgL5gNMKCCkHgvL5bJfF1eDto7CZrBMeog4R7sXehHShXl1WoIHHps42L3Zsw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711986850; c=relaxed/simple; bh=S6fJM3Kz4JOL994prCV8jwmQpf1w3CaIsANhSjwCwbg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iCWNeVIwNcGalcJGiU+iDDuInRbF1mUozouxlZHiNr4sU8pZSbfUEq9B5AijwY4h5I9YN1IZ1Fw7ENKwgWy59vAO9iskYmHa/TBGK3KfE3chCEFiz22o8l7ePH/grDB7HGYfa6Oorx8EDKmUz+xfaU7sbG66shNQRRn+xwz6dFE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=AThZfYsB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="AThZfYsB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 375FDC433C7; Mon, 1 Apr 2024 15:54:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1711986850; bh=S6fJM3Kz4JOL994prCV8jwmQpf1w3CaIsANhSjwCwbg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AThZfYsBzn47uE+VKAL+8Ua7xt1G6ErtZ3BREUmOxKyON8/SKG3+gbRnjGOjUxxT6 RK0791BNugRB15vJ3DOQpqzYzjkJJMfLEd87cHQbl7QIA/epg1Q2b8YR35I2+c+hF3 ER2WYvqLB2ChY3al7xKyNTy90037Hzw2ccsPGkXA= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Quentin Schulz , Heiko Stuebner , Stable@vger.kernel.org, Jonathan Cameron , Sasha Levin Subject: [PATCH 6.8 065/399] iio: adc: rockchip_saradc: use mask for write_enable bitfield Date: Mon, 1 Apr 2024 17:40:31 +0200 Message-ID: <20240401152551.126611547@linuxfoundation.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240401152549.131030308@linuxfoundation.org> References: <20240401152549.131030308@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.8-stable review patch. If anyone has any objections, please let me know. ------------------ From: Quentin Schulz [ Upstream commit 5b4e4b72034f85f7a0cdd147d3d729c5a22c8764 ] Some of the registers on the SARADCv2 have bits write protected except if another bit is set. This is usually done by having the lowest 16 bits store the data to write and the highest 16 bits specify which of the 16 lowest bits should have their value written to the hardware block. The write_enable mask for the channel selection was incorrect because it was just the value shifted by 16 bits, which means it would only ever write bits and never clear them. So e.g. if someone starts a conversion on channel 5, the lowest 4 bits would be 0x5, then starts a conversion on channel 0, it would still be 5. Instead of shifting the value by 16 as the mask, let's use the OR'ing of the appropriate masks shifted by 16. Note that this is not an issue currently because the only SARADCv2 currently supported has a reset defined in its Device Tree, that reset resets the SARADC controller before starting a conversion on a channel. However, this reset is handled as optional by the probe function and thus proper masking should be used in the event an SARADCv2 without a reset ever makes it upstream. Fixes: 757953f8ec69 ("iio: adc: rockchip_saradc: Add support for RK3588") Signed-off-by: Quentin Schulz Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20240223-saradcv2-chan-mask-v1-2-84b06a0f623a@theobroma-systems.com Cc: Signed-off-by: Jonathan Cameron Signed-off-by: Sasha Levin --- drivers/iio/adc/rockchip_saradc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c index 2da8d6f3241a1..1c0042fbbb548 100644 --- a/drivers/iio/adc/rockchip_saradc.c +++ b/drivers/iio/adc/rockchip_saradc.c @@ -102,12 +102,12 @@ static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn) writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC); writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC); val = FIELD_PREP(SARADC2_EN_END_INT, 1); - val |= val << 16; + val |= SARADC2_EN_END_INT << 16; writel_relaxed(val, info->regs + SARADC2_END_INT_EN); val = FIELD_PREP(SARADC2_START, 1) | FIELD_PREP(SARADC2_SINGLE_MODE, 1) | FIELD_PREP(SARADC2_CONV_CHANNELS, chn); - val |= val << 16; + val |= (SARADC2_START | SARADC2_SINGLE_MODE | SARADC2_CONV_CHANNELS) << 16; writel(val, info->regs + SARADC2_CONV_CON); } -- 2.43.0