From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AFB91F5FA; Thu, 11 Apr 2024 10:09:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712830187; cv=none; b=l4/RsQzc2psR6EyJxbZE34PTy+ElYT/yQ43h1P7nWQn3j8m+8eZ/04uG0d720iLXv+ODmliSKR+p9tV/OACiBtrfyMsynLzcdQKhfmnOLSw+DhKS6Hp7DJKCdNVlYv4d3zjYZlXS7rpU0iuMeayIx4loAJwVfMm4w8CnmWMHMnA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712830187; c=relaxed/simple; bh=WwyeADEeMw1Gg2vxlnGLqulJrBtuuF972j9T27kkmq8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KxJuDVBlAoyz04BLGIjahiwm3Vq3CdKxKkZWy9hl3kqkzZjV2wMseT8gd5yQ/LYzFsoEPJCy3sg+B7s32FwhFjE0aZcfTPj0FgSiHvpEy1kw5QIC7BDKJv225fTp1IfRNDr78voShXGkCQNZoQ7NtXYeOMonvoBIAHXukl4zcSs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=V/1yRuh0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="V/1yRuh0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D6534C43390; Thu, 11 Apr 2024 10:09:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1712830187; bh=WwyeADEeMw1Gg2vxlnGLqulJrBtuuF972j9T27kkmq8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V/1yRuh070I1JmPC73DJn2dOIfk79RAowK8Sv+PSlGGl+jnD0hLeGII0quqsf5A8O 4C1j1BD+KWdW1ykjfySZFtImPtNsTKUv9pQrXmPklLuRiNiQZYpLkHuRgnNmqJGAB7 8kNkmq0LnywhZwjdEL5Ev0gUkaEjLCO0QEKasxEk= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Chaitanya Dhere , Alvin Lee , Tom Chung , Sohaib Nadeem , Daniel Wheeler , Alex Deucher , Sasha Levin Subject: [PATCH 6.8 065/143] drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz Date: Thu, 11 Apr 2024 11:55:33 +0200 Message-ID: <20240411095422.873221496@linuxfoundation.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240411095420.903937140@linuxfoundation.org> References: <20240411095420.903937140@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.8-stable review patch. If anyone has any objections, please let me know. ------------------ From: Sohaib Nadeem [ Upstream commit d46fb0068c54d3dc95ae8298299c4d9edb0fb7c1 ] [why] Originally, PMFW said min FCLK is 300Mhz, but min DCFCLK can be increased to 400Mhz because min FCLK is now 600Mhz so FCLK >= 1.5 * DCFCLK hardware requirement will still be satisfied. Increasing min DCFCLK addresses underflow issues (underflow occurs when phantom pipe is turned on for some Sub-Viewport configs). [how] Increasing DCFCLK by raising the min_dcfclk_mhz Reviewed-by: Chaitanya Dhere Reviewed-by: Alvin Lee Acked-by: Tom Chung Signed-off-by: Sohaib Nadeem Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index a0a65e0991041..ba76dd4a2ce29 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -2760,7 +2760,7 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk struct _vcs_dpi_voltage_scaling_st entry = {0}; struct clk_limit_table_entry max_clk_data = {0}; - unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299; + unsigned int min_dcfclk_mhz = 399, min_fclk_mhz = 599; static const unsigned int num_dcfclk_stas = 5; unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; -- 2.43.0